JAJSP58 September   2022 TPS544C26

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 Set the Output Voltage and VID Table

The TPS544C26 device offers VOUT adjustment through either SVID interface (for example, VID related SVID commands) or I2C interface (for example, (A6h) VOUT_CMD register). To allow flexibility and also avoid conflict, the device utilizes VOUT_CTRL[1:0] bits in register (A0h) SYS_CFG_USER1 to select which interface or method controls the VOUT level during the soft-start and nominal operation target. Table 7-4 describes more details.

The VOUT_CTRL value is latched after the power conversion is enabled (EN=high). While the device is enabled, a write to VOUT_CTRL bits are acknowledged but the VOUT control method does not change until an EN toggle happens.

Table 7-4 VOUT Control Method
VOUT_CTRLVOUT Control MethodStart-upNominal OperationMaximum VOUT LimitFurther Restrictions
VOUTVOUT OffsetVOUTVOUT Offset
00bSVID onlySet by Vboot in I2C register (C2h) PROTOCOL_ID_SVIDSet by SVID register (33h) OFFSET. This offset is always zero before EN=highSet by SVID commands (such as SetVID, SetWP)Set by SVID register (33h) OFFSETSVID register 09h-0Ah VIDoMAXI2C register (A6h) VOUT_CMD is always ignored (ACK response for a write but does nothing). I2C register (A8h) I2C_OFFSET is de-activated (NACK response for a write)
01bSVID + I2CSet by Vboot in I2C register (C2h) PROTOCOL_ID_SVIDSet by I2C register (A8h) I2C_OFFSETSet by SVID commands (such as SetVID, SetWP)Set by I2C register (A8h) I2C_OFFSET. A new I2C_OFFSET value does not take effect immediately. Instead, the new value takes effect on the next start-upSVID register 09h-0Ah VIDoMAXI2C register (A6h) VOUT_CMD is always ignored (ACK response for a write but does nothing). SVID register (33h) OFFSET is ignored (ACK response for a write but does nothing)
10b or 11bI2C onlySet by I2C register (A6h) VOUT_CMDSet by I2C register (A8h) I2C_OFFSETSet by I2C register (A6h) VOUT_CMD. A new VOUT_CMD value takes effect immediately.Set by I2C register (A8h) I2C_OFFSET. A new I2C_OFFSET value takes effect immediately.17E in hexSVID SetVID/SetWP command and SVID register (33h) OFFSET are always ignored (ACK response for a write but does nothing)

With VOUT_CTRL[1:0] = 00b or 01b (VOUT controlled by SVID), the initial output voltage can be set by the Vboot during initial power up, with the range from 0.75 V to 1.8 V (see Table 7-5). Vboot value can be adjusted through a write into the Vboot filed in I2C register Section 7.6.63. Upon the acknowledge of the I2C write, the new Vboot value is automatically copied into SVID (26h) Vboot register. With a successful I2C (15h) STORE_USER_ALL command, this new value is saved into NVM. During next power-on sequence, TPS544C26 loads the saved Vboot value from NVM into both I2C Vboot field and SVID (26h) Vboot register. Once the soft-start ramp finishes, the output voltage can be changed by sending SetVID or SetWP command to the device, or sending a new SVID OFFSET value to the device.

With VOUT_CTRL[1:0] = 10b or 11b (VOUT controlled by I2C), the initial output voltage can be set by the register (A6h) VOUT_CMD during initial power up. The available VOUT_CMD range is 0.25 V to 1.52 V for PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV), and 0.50 V to 3.04 V for PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV). Once the soft-start ramp finishes, the output voltage can be changed by sending new value to I2C register (A6h) VOUT_CMD, or sending a new (A8h) I2C_OFFSET value to the device. Upon the acknowledge of a I2C write into I2C register (A6h) VOUT_CMD or (A8h) I2C_OFFSET, the new value takes effect immediately. With a successful I2C (15h) STORE_USER_ALL command, this new value is saved into NVM. During next power-on sequence, TPS544C26 loads the saved value from NVM and use that value for the soft-start.

Table 7-5 Vboot Settings
Vboot in (C2h) PROTOCOL_ID_SVID VID code1 (Hex) Vboot (V) PROTOCOL_ID in (C2h) PROTOCOL_ID_SVID
0000b 00h 0 Must set PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV)
0001b 65h 0.75
0010b 6Fh 0.80
0011b 79h 0.85
0100b 83h 0.90
0101b 8Dh 0.95
0110b 97h 1.00
0111b A1h 1.05
1000b ABh 1.10
1001b AFh 1.20
1010b C9h 1.25
1011b DDh 1.35
1100b FBh 1.50
1101b 6Fh 1.60 Must set PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV)
1110b 79h 1.70
1111b 83h 1.80
  1. VID code is not directly visiable to customer but shows up in I2C register (A7h) VID_SETTING and SVID register (31h) VID_SETTING.

TPS544C26 always follows below VID table when setting output voltage, no matter through SVID interface or I2C interface. When setting output voltage, aligning the VOUT value with PROTOCOL_ID (5 mV or 10 mV) accordantly is important. An incorrect selection on the VOUT and PROTOCOL_ID value can result in a NACK response for the write into (C2h) PROTOCOL_ID_SVID register. For example, a configuration of Vboot = 1.8 V and PROTOCOL_ID = 01b (VOUT step 5 mV) results in a NACK response. Another example with VOUT_CTRL[1:0] = 10b or 11b (VOUT controlled by I2C), setting VOUT_CMD to 2.5 V requires PROTOCOL_ID = 00b or 11b (VOUT step 10 mV) and thus requires Vboot to be one of the 3 options of 1.6 V, 1.7 V and 1.8 V. Even the Vboot value does not affect VOUT level for VOUT_CTRL[1:0] = 10b or 11b selection, a suitable Vboot value is needed to pass the error check on Vboot and PROTOCOL_ID fields.

Table 7-6 VID Table for Output Voltage
VID code (Hex)

VOUT (V)

5-mV Step

VOUT (V)

10-mV Step

 VID Code (Hex)

VOUT (V)

5-mV Step

VOUT (V)

10-mV Step

 VID Code (Hex)

VOUT (V)

5-mV Step

VOUT (V)

10-mV Step

 VID Code (Hex)

VOUT (V)

5-mV Step

VOUT (V)

10-mV Step
00 0.000 0.00 40 0.565 1.13 80 0.885 1.77 C0 1.205 2.41
01 0.250 0.50 41 0.570 1.14 81 0.890 1.78 C1 1.210 2.42
02 0.255 0.51 42 0.575 1.15 82 0.895 1.79 C2 1.215 2.43
03 0.260 0.52 43 0.580 1.16 83 0.900 1.80 C3 1.220 2.44
04 0.265 0.53 44 0.585 1.17 84 0.905 1.81 C4 1.225 2.45
05 0.270 0.54 45 0.590 1.18 85 0.910 1.82 C5 1.230 2.46
06 0.275 0.55 46 0.595 1.19 86 0.915 1.83 C6 1.235 2.47
07 0.280 0.56 47 0.600 1.20 87 0.920 1.84 C7 1.240 2.48
08 0.285 0.57 48 0.605 1.21 88 0.925 1.85 C8 1.245 2.49
09 0.290 0.58 49 0.610 1.22 89 0.930 1.86 C9 1.250 2.50
0A 0.295 0.59 4A 0.615 1.23 8A 0.935 1.87 CA 1.255 2.51
0B 0.300 0.60 4B 0.620 1.24 8B 0.940 1.88 CB 1.260 2.52
0C 0.305 0.61 4C 0.625 1.25 8C 0.945 1.89 CC 1.265 2.53
0D 0.310 0.62 4D 0.630 1.26 8D 0.950 1.90 CD 1.270 2.54
0E 0.315 0.63 4E 0.635 1.27 8E 0.955 1.91 CE 1.275 2.55
0F 0.320 0.64 4F 0.640 1.28 8F 0.960 1.92 CF 1.280 2.56
10 0.325 0.65 50 0.645 1.29 90 0.965 1.93 D0 1.285 2.57
11 0.330 0.66 51 0.650 1.30 91 0.970 1.94 D1 1.290 2.58
12 0.335 0.67 52 0.655 1.31 92 0.975 1.95 D2 1.295 2.59
13 0.340 0.68 53 0.660 1.32 93 0.980 1.96 D3 1.300 2.60
14 0.345 0.69 54 0.665 1.33 94 0.985 1.97 D4 1.305 2.61
15 0.350 0.70 55 0.670 1.34 95 0.990 1.98 D5 1.310 2.62
16 0.355 0.71 56 0.675 1.35 96 0.995 1.99 D6 1.315 2.63
17 0.360 0.72 57 0.680 1.36 97 1.000 2.00 D7 1.320 2.64
18 0.365 0.73 58 0.685 1.37 98 1.005 2.01 D8 1.325 2.65
19 0.370 0.74 59 0.690 1.38 99 1.010 2.02 D9 1.330 2.66
1A 0.375 0.75 5A 0.695 1.39 9A 1.015 2.03 DA 1.335 2.67
1B 0.380 0.76 5B 0.700 1.40 9B 1.020 2.04 DB 1.340 2.68
1C 0.385 0.77 5C 0.705 1.41 9C 1.025 2.05 DC 1.345 2.69
1D 0.390 0.78 5D 0.710 1.42 9D 1.030 2.06 DD 1.350 2.70
1E 0.395 0.79 5E 0.715 1.43 9E 1.035 2.07 DE 1.355 2.71
1F 0.400 0.80 5F 0.720 1.44 9F 1.040 2.08 DF 1.360 2.72
20 0.405 0.81 60 0.725 1.45 A0 1.045 2.09 E0 1.365 2.73
21 0.410 0.82 61 0.730 1.46 A1 1.050 2.10 E1 1.370 2.74
22 0.415 0.83 62 0.735 1.47 A2 1.055 2.11 E2 1.375 2.75
23 0.420 0.84 63 0.740 1.48 A3 1.060 2.12 E3 1.380 2.76
24 0.425 0.85 64 0.745 1.49 A4 1.065 2.13 E4 1.385 2.77
25 0.430 0.86 65 0.750 1.50 A5 1.070 2.14 E5 1.390 2.78
26 0.435 0.87 66 0.755 1.51 A6 1.075 2.15 E6 1.395 2.79
27 0.440 0.88 67 0.760 1.52 A7 1.080 2.16 E7 1.400 2.80
28 0.445 0.89 68 0.765 1.53 A8 1.085 2.17 E8 1.405 2.81
29 0.450 0.90 69 0.770 1.54 A9 1.090 2.18 E9 1.410 2.82
2A 0.455 0.91 6A 0.775 1.55 AA 1.095 2.19 EA 1.415 2.83
2B 0.460 0.92 6B 0.780 1.56 AB 1.100 2.20 EB 1.420 2.84
2C 0.465 0.93 6C 0.785 1.57 AC 1.105 2.21 EC 1.425 2.85
2D 0.470 0.94 6D 0.790 1.58 AD 1.110 2.22 ED 1.430 2.86
2E 0.475 0.95 6E 0.795 1.59 AE 1.115 2.23 EE 1.435 2.87
2F 0.480 0.96 6F 0.800 1.60 AF 1.120 2.24 EF 1.440 2.88
30 0.485 0.97 70 0.805 1.61 B0 1.125 2.25 F0 1.445 2.89
31 0.490 0.98 71 0.810 1.62 B1 1.130 2.26 F1 1.450 2.90
32 0.495 0.99 72 0.815 1.63 B2 1.135 2.27 F2 1.455 2.91
33 0.500 1.00 73 0.820 1.64 B3 1.140 2.28 F3 1.460 2.92
34 0.505 1.01 74 0.825 1.65 B4 1.145 2.29 F4 1.465 2.93
35 0.510 1.02 75 0.830 1.66 B5 1.150 2.30 F5 1.470 2.94
36 0.515 1.03 76 0.835 1.67 B6 1.155 2.31 F6 1.475 2.95
37 0.520 1.04 77 0.840 1.68 B7 1.160 2.32 F7 1.480 2.96
38 0.525 1.05 78 0.845 1.69 B8 1.165 2.33 F8 1.485 2.97
39 0.530 1.06 79 0.850 1.70 B9 1.170 2.34 F9 1.490 2.98
3A 0.535 1.07 7A 0.855 1.71 BA 1.175 2.35 FA 1.495 2.99
3B 0.540 1.08 7B 0.860 1.72 BB 1.180 2.36 FB 1.500 3.00
3C 0.545 1.09 7C 0.865 1.73 BC 1.185 2.37 FC 1.505 3.01
3D 0.550 1.10 7D 0.870 1.74 BD 1.190 2.38 FD 1.510 3.02
3E 0.555 1.11 7E 0.875 1.75 BE 1.195 2.39 FE 1.515 3.03
3F 0.560 1.12 7F 0.880 1.76 BF 1.200 2.40 FF 1.520 3.04