JAJSHM1B July   2008  – June 2019 TPS5450-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図と効率曲線
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Dissipation Ratings
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Frequency
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Enable (ENA) and Internal Slow Start
      4. 7.3.4  Undervoltage Lockout (UVLO)
      5. 7.3.5  Output Feedback (VSENSE) and Internal Compensation
      6. 7.3.6  Voltage Feedforward
      7. 7.3.7  Pulse-Width-Modulation (PWM) Control
      8. 7.3.8  Overcurrent Limiting
      9. 7.3.9  Overvoltage Protection
      10. 7.3.10 Thermal Shutdown
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Boost Capacitor (BOOT)
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Output Filter Components
          1. 8.2.2.5.1 Inductor Selection
          2. 8.2.2.5.2 Capacitor Selection
        6. 8.2.2.6  Output Voltage Setpoint
        7. 8.2.2.7  Boot Capacitor
        8. 8.2.2.8  Catch Diode
        9. 8.2.2.9  Output Voltage Limitations
        10. 8.2.2.10 Internal Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
    3. 9.3 Thermal Calculations
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 10.2 開発サポート
      1. 10.2.1 WEBENCH®ツールによるカスタム設計
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 コミュニティ・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.9 Output Voltage Limitations

Due to the internal design of the TPS5450-Q1, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by:

Equation 13. TPS5450-Q1 q13_voutmax_lvs632.gif

where

  • VINMIN = minimum input voltage
  • IOMAX = maximum load current
  • VD = catch diode forward voltage
  • RL= output inductor series resistance

This equation assumes maximum on resistance for the internal high side FET.

The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by:

Equation 14. TPS5450-Q1 q14_voutmin_lvs632.gif

where

  • VINMAX = maximum input voltage
  • IOMIN = minimum load current
  • VD = catch diode forward voltage
  • RL= output inductor series resistance

This equation assumes nominal on resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checked to ensure proper functionality.