JAJSBU6B May   2013  – October 2023 TPS54531

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Voltage Reference (Vref)
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 7.3.5  Programmable Slow Start Using SS Pin
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation
      8. 7.3.8  Current-Mode Compensation Design
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Eco-mode
      2. 7.4.2 Operation With VIN < 3.5 V
      3. 7.4.3 Operation With EN Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Voltage Set Point
        4. 8.2.2.4  Undervoltage Lockout Set Point
        5. 8.2.2.5  Input Capacitors
        6. 8.2.2.6  Output Filter Components
          1. 8.2.2.6.1 Inductor Selection
          2. 8.2.2.6.2 Capacitor Selection
        7. 8.2.2.7  Compensation Components
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Catch Diode
        10. 8.2.2.10 Slow-Start Capacitor
        11. 8.2.2.11 Output Voltage Limitations
        12. 8.2.2.12 Power Dissipation Estimate
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Electromagnetic Interference (EMI) Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.11 Output Voltage Limitations

Because of the internal design of the TPS54531 device, any give voltage has both upper and lower output voltage limits for any given input voltage. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is calculated with Equation 20. The equation assumes the maximum ON resistance for the internal high-side FET.

Equation 20. V O M A X = 0.91 × V I N M I N - I O M A X × R D S O N M A X + V D - I O M A X × R L - V D

where

  • VIN(MIN) = Minimum input voltage
  • IO(MAX) = Maximum load current
  • VD = Catch diode forward voltage
  • RL = Output inductor series resistance

The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 21.

Equation 21. VOMIN=0.089×VINMAX-IOMIN×RDSONMIN+VD-IOMIN×RL-VD

where

  • VIN(MAX) = Maximum input voltage
  • IO(MIN) = Minimum load current
  • VD = Catch diode forward voltage
  • RL = Output inductor series resistance

This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device must be carefully checked to ensure proper functionality.