JAJSHH0E August   2013  – May 2019 TPS54618-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation and Output Current
      3. 8.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Soft-Start Pin
      9. 8.3.9  Sequencing
      10. 8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 8.3.11 Overcurrent Protection
      12. 8.3.12 Frequency Shift
      13. 8.3.13 Reverse Overcurrent Protection
      14. 8.3.14 Synchronize Using the RT/CLK Pin
      15. 8.3.15 Power Good (PWRGD Pin)
      16. 8.3.16 Overvoltage Transient Protection
      17. 8.3.17 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Simple Small Signal Model for Peak Current Mode Control
      2. 8.4.2 Small Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Step One: Select the Switching Frequency
        3. 9.2.2.3 Step Two: Select the Output Inductor
        4. 9.2.2.4 Step Three: Choose the Output Capacitor
        5. 9.2.2.5 Step Four: Select the Input Capacitor
        6. 9.2.2.6 Step Five: Choose the Soft-Start Capacitor
        7. 9.2.2.7 Step Six: Select the Bootstrap Capacitor
        8. 9.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
          1. 9.2.2.8.1 Output Voltage Limitations
        9. 9.2.2.9 Step Nine: Select Loop Compensation Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation Estimate
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
      2. 12.1.2 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 200 2000 kHz
Switching frequency Rt = 400 kΩ 400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
Minimum CLK pulse width 75 ns
RT/CLK voltage R(RT/CLK) = 400 kΩ 0.5 V
RT/CLK high threshold 1.6 2.2 V
RT/CLK low threshold 0.4 0.6 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns
PLL lock in time Measure at 500 kHz 42 μs
PH (PH PIN)
Minimum ON-time Measured at 50% points on PH, IOUT = 3 A 75 ns
Measured at 50% points on PH, VIN = 6 V,
IOUT = 0 A		 120
Minimum OFF-time Prior to skipping off pulses, BOOT-PH = 2.95 V,
IOUT = 3 A		 60 ns
Rise time VIN = 6 V, 6 A 2.25 V/ns
Fall time VIN = 6 V, 6 A 2