JAJSBO6B June   2012  – May 2019 TPS54678

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation and Output Current
      3. 8.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Soft-Start Pin
      9. 8.3.9  Sequencing
      10. 8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side Overcurrent Protection
        2. 8.3.11.2 Low-Side Overcurrent Protection
      12. 8.3.12 Safe Start-Up into Prebiased Outputs
      13. 8.3.13 Synchronize Using the RT/CLK Pin
      14. 8.3.14 Power Good (PWRGD Pin)
      15. 8.3.15 Overvoltage Transient Protection
      16. 8.3.16 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Small Signal Model for Loop Response
      2. 8.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 8.4.3 Small Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Step One: Select the Switching Frequency
        3. 9.2.2.3 Step Two: Select the Output Inductor
        4. 9.2.2.4 Step Three: Choose the Output Capacitor
        5. 9.2.2.5 Step Four: Select the Input Capacitor
        6. 9.2.2.6 Step Five: Choose the Soft-Start Capacitor
        7. 9.2.2.7 Step Six: Select the Bootstrap Capacitor
        8. 9.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
          1. 9.2.2.8.1 Output Voltage Limitations
        9. 9.2.2.9 Step Nine: Select Loop Compensation Components
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Additional Information About Application Curves
          1. 9.2.3.1.1 Efficiency
          2. 9.2.3.1.2 Voltage Ripple Measurements
          3. 9.2.3.1.3 Start-Up and Shutdown Waveforms
          4. 9.2.3.1.4 Hiccup Mode Current Limit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation Estimate
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 2.95 6 V
Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V 1 3 µA
Operating non-switching supply current VSENSE = 0.6 V, VIN = 5 V, 25°C, fSW = 500 kHz 570 800 µA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.3 V
Enable threshold Falling 1.18 V
Input current Enable threshold + 50 mV –3.5 µA
Input current Enable threshold – 50 mV –0.70 µA
VOLTAGE REFERENCE
Voltage reference 2.95 V ≤ VIN ≤ 6 V, –40°C < TJ < 150°C 0.594 0.600 0.606 V
MOSFET
High-side switch resistance BOOT-PH = 5 V 12 25 mΩ
High-side switch resistance BOOT-PH = 2.95 V 17 33
Low-side switch resistance BOOT-PH = 5 V 12 25 mΩ
Low-side switch resistance BOOT-PH = 2.95 V 17 33
ERROR AMPLIFIER
Input current 7 nA
Error amplifier transconductance (gm) –2 µA < I(COMP) < 2 µA V(COMP) = 1 V 245 umhos
Error amplifier transconductance (gm) during slow-start –2 µA < I(COMP) < 2 µA V(COMP) = 1 V, V(VSENSE) = 0.4 V 80 umhos
Error amplifier source and sink V(COMP) = 1 V 100-mV overdrive ±20 µA
COMP to Iswitch gm 20 A/V
CURRENT LIMIT
Current limit threshold Fs = 500 KHz 9.5 10.5 11.5 A
Cycles before entering hiccup during overcurrent 512 cycles
Hiccup cycles 16384 cycles
Low-side sourcing current threshold 7 8.5 10.5 A
Low-side FET reverse current protection 4 A
THERMAL SHUTDOWN
Thermal shutdown 170 °C
Hysteresis 15 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 200 2000 kHz
Switching frequency Rt = 82.5 kΩ 400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
Minimum CLK pulse width 75 ns
RT/CLK voltage R(RT/CLK) = 82.5 kΩ 0.5 V
RT/CLK high threshold 1.6 2.2 V
RT/CLK low threshold 0.4 0.6 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 55 ns
PLL lock in time Measure at 500 kHz 40 µs
PH (PH PIN)
Minimum ON-time Measured at 50% points on PH. IOUT = 3 A 85 110 ns
Measured at 50% points on PH. IOUT = 0 A 100 ns
Minimum OFF-time Prior to skipping off pulses,
BOOT-PH = 3 V, IOUT = 3 A		 70 ns
Rise and fall dV/dT BOOT-PH = 3 V; IO = 6 A 1.5 V/ns
BOOT (BOOT PIN)
Charging resistor VIN = 6 V, BOOT-PH = 6 V 7 Ω
BOOT-PH UVLO VIN = 3.3 V 2.2 V
SLOW START AND TRACKING (SS/TR PIN)
Charge current V(SS/TR) < 0.15 V 47 µA
V(SS/TR) > 0.15 V 2.2
SS/TR to VSENSE matching VIN = 3.3 V 60 mV
SS/TR to reference crossover 98% nominal 0.8 V
SS/TR discharge voltage (overload) VSENSE = 0 V 4.5 mV
SS/TR discharge to current (overload) VSENSE = 0 V; V(SS/TR) = 4 V 95 µA
SS/TR discharge current (UVLO, EN, thermal fault) VIN = 3 V; V(SS/TR) = 4 V 925 µA
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (Fault) 91 % VREF
VSENSE rising (Good) 93 % VREF
VSENSE rising (Fault) 105 % VREF
VSENSE falling (Good) 103 % VREF
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 2 nA
ON-Resistance VIN = 5 V 65 120 Ω
Output low I(PWRGD) = 2.5 mA 0.2 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 µA 1.2 1.5 V