8.1 Overview

The TPS54678 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated N-channel MOSFETs. To improve the performance during line and load transients the device implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock.

The TPS54678 has a typical default start-up voltage of 2.4 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external resistors. In addition, the pullup current provides a default condition when the EN pin is floating for the device to operate. The total operating current for the TPS54678 is typically 570 µA when not switching and under no load. When the device is disabled, the supply current is less than 3 µA.

The integrated 12-mΩ MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 6 amperes. The TPS54678 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54678 to operate approaching 100%. The output voltage can be stepped down to as low as the 0.60-V reference.

TPS54678 features monotonic start-up under prebias conditions. The low-side FET turns on for a short time period every cycle before the output voltage reaches the prebiased voltage. This ensures the boot cap has enough charge to turn on the top FET when the output voltage reaches the prebiased voltage.

The TPS54678 has a power good comparator (PWRGD) with 2% hysteresis.

The TPS54678 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power good comparator. When the regulated output voltage is greater than 105% of the nominal voltage, the overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output voltage is lower than 103%.

The SS/TR (slow-start or tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin for slow-start. The SS/TR pin is discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault or disabled condition. To optimize the output startup waveform, two levels of SS current are implemented.

To reduce the power dissipation of TPS54678 during overcurrent event, the hiccup protection is implemented beyond the cycle-by-cycle protection.