JAJSGG4A November 2018 – December 2018 TPS546D24
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | PGD/RST_B | I/O | Open-drain power good or reset#, As determined by user accessible bit (See in PMBUS Command detailed descriptions) . The default pin function is an open drain power-good indicator. |
| 2 | PMB_DATA | I/O | PMBus DATA pin. See PMBus specification. |
| 3 | PMB_CLK | I | PMBus CLK pin. See PMBus specification. |
| 4 | BP1V5 | O | Output of the 1.5-V internal regulator. This regulator powers the digital circuitry and should be bypassed with a minimum of 1 µF to DRTN. BP1V5 is not designed to power external circuit. |
| 5 | DRTN | — | Digital bypass return for bypass capacitor for BP1V5. Internally Connected to AGND. Do not Connect to PGND or AGND. |
| 6 | SMB_ALRT | O | SMBus alert pin. See SMBus specification. |
| 7 | BOOT | I | Bootstrap pin for the internal flying high side driver. Connect a typical 100 nF from this pin to SW. To reduce the voltage spike at SW, an optional BOOT resistor of up to 8 Ω may be placed in series with the BOOT capacitor to slow down turn-on of the high-side FET. |
| 8 | SW | I/O | Switched power output of the device. Connect the output averaging filter and bootstrap to this group of pins. |
| 9 | |||
| 10 | |||
| 11 | |||
| 12 | |||
| 13 | PGND | — | Power stage ground return. These pins are internally connected to the thermal pad. |
| 14 | |||
| 15 | |||
| 16 | |||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | |||
| 21 | PVIN | I | Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. |
| 22 | |||
| 23 | |||
| 24 | |||
| 25 | |||
| 26 | AVIN | I | Input power to the controller. Bypass with a minimum 1-µF ceramic capacitor to PGND. If AVIN is connected to the same input as PVIN or VDD5, a minimum 10-µs R-C filter is recommended to reduce switching noise on AVIN. |
| 27 | EN/UVLO | I | Enable switching as the PMBus CONTROL pin. EN/UVLO can also be connected to a resistor divider to program input voltage UVLO. |
| 28 | VDD5 | O | Output of the 5-V internal regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 4.7 µF to PGND at the thermal pad. Low impedance bypassing of this pin to PGND is critical. |
| 29 | MSEL2 | I | Connect this pin to a resistor divider between BP1V5 and AGND for different options of soft-start time, overcurrent fault limit, and multi-phase information. See section |
| 30 | VSEL | I | Connect this pin to a resistor divider between BP1V5 and AGND for different options of internal voltage feedback divider and default output voltage. See section. |
| 31 | ADRSEL | I | Connect this pin to a resistor divider between BP1V5 and AGND for different options of PMBus addresses and frequency sync (including determination of SYNC pin as SYNC IN or SYNC OUT function). See section. |
| 32 | MSEL1 | I | Connect this pin to a resistor divider between BP1V5 and AGND for different options of switching frequency and internal compensation parameters. See section. |
| 33 | VOSNS | I | The positive input of the remote sense amplifier. For a standalone device or the loop master device in a multi-phase configuration, connect VOSNS pin to the output voltage at the load. For the loop slave device in a multi-phase configuration, the remote sense amplifier is not required for output voltage sensing or regulation, this pin can be left floating. |
| 34 | GOSNS/SLAVE | I | The negative input of the remote sense amplifier for loop master device or should be pulled up high to indicate loop slave. For standalone device or the loop master device in a multi-phase configuration, connect GOSNS pin to the ground at the load. For the loop slave device in a multi-phase configuration, the GOSNS pin must be pulled up to BP1V5 to indicate the device a loop slave. |
| 35 | VSHARE | I/O | Voltage sharing signal for multi-phase operation. For stand-alone device, the VSHARE pin must be left floating. |
| 36 | NC | - | Not internally connected. Pin can be left floating or connected to PGND at the thermal pad. |
| 37 | AGND | - | Analog ground return for controller. Connect the AGND pin directly to the thermal pad on the PCB board. |
| 38 | SYNC | I/O | For frequency synchronization, can be programmed as SYNC IN or SYNC OUT pin by ADRSEL pin or the PMBus Command. The SYNC pin can be left floating when not used. |
| 39 | BCX_CLK | I/O | Clock for back-channel communications between stacked devices. |
| 40 | BCX_DAT | I/O | Data for back-channel communications between stacked devices. |
| — | Thermal pad | — | Package thermal pad, internally connected to PGND. The thermal pad must have adequate solder coverage for proper operation. |