TPS546E25 device has an internal 4.5V LDO featuring input from PVIN and output to VCC pin. When the PVIN voltage rises, the internal LDO is enabled automatically and starts regulating LDO output voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry in controller side and the VDRV voltage provides the supply voltage for the power stage side.

Both the VCC pin and the VDRV pin must be bypassed with a 2.2μF, at least 6.3V rating ceramic capacitor. The VCC pin decoupling capacitor is required to refer to AGND to provide a clean ground for the analog circuitry in controller. The VDRV pin decoupling capacitor is required to refer to PGND to minimize the parasitic loop inductance for the driver circuitry in the power stage. TI highly recommends placing a 1Ω resistor between the VCC pin and VDRV pin to form an RC filter, thus the noise impact from power stage is reduced.

An external bias ranging 4.75V to 5.30V can be connected to the VDRV pin and VCC pin and power the IC. This connection enhances the efficiency of the converter because the VDRV and VCC power supply current now runs off this external bias instead of the internal linear regulator.

A VDRV UVLO circuit monitors the VDRV pin voltage and disables the switching when VDRV falls below the VDRV UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of the device.

Considerations when using an external bias on the VDRV and VCC pin are shown below:

• Connect the external bias to VDRV pin directly. Place a 1Ω resistor between the VCC pin and VDRV pin, then VCC is powered through the 1Ω filtering resistor.
• A good power-up sequence is: the external 5V bias is applied to VDRV pin first (VCC pin is also powered by the external bias through the 1Ω filtering resistor), then the 12V bus applied on PVIN pin, and then CTRL signal goes high.