JAJSQT1 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address | D4h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | Unsigned Binary (2 bytes) |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly |
This command contains feedback compensation settings for the regulated rail.
Return to Supported PMBus Commands.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R/W | R/W | R/W | R/W | R | R | R | R |
| GAIN | 0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R | R/W | R/W | R/W | R | R/W | R/W |
| FRC_IN_TIME | 0 | INT_TIME | 0 | SEL_RAMP | |||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:12 | GAIN | R/W | NVM | These bits determine the AC Gain setting. 0000b: Gain of 3V/V 0001b: Gain of 5V/V 0010b: Gain of 10V/V 0011b: Gain of 15V/V 0100b: Gain of 20V/V 0101b: Gain of 25V/V 0110b: Gain of 30V/V 0111b: Gain of 35V/V 1000b: Gain of 40V/V 1001b: Gain of 50V/V 1010b: Gain of 60V/V 1011b: Gain of 70V/V |
| 11:8 | 0 | R | 0000b | Not supported and always 0. |
| 7 | FRC_INT_TIME | R/W | NVM | Force integrator time constant from NVM settings. 0b: Makes the INT_TIME[2:0] bits in this register read-only and are populated based on the existing live data in the (33h) FREQUENCY_SWITCH register, as specified by the look-up table INT_TIME below:
1b: Makes the INT_TIME [2:0] bits in this register writable and initialized from the associated NVM backup |
| 6 | 0 | R | 0b | Not supported and always 0. |
| 5:3 | INT_TIME | R/W | NVM | Integrator time constand setting. 000b = 0.25μs 001b = 1μs 010b = 3μs 011b = 4.5μs 100b = 6.25μs 101b = 8μs 110b = 10μs 111b = 20μs |
| 2 | 0 | R | 0b | Not supported and always 0. |
| 1:0 | SEL_RAMP | R/W | NVM | Ramp amplitude/slope setting. These bits determine the ramp
amplitude/slope. 00b = 60mV 01b = 120mV 10b = 180mV 11b = 240mV |
Data Validity
Attempts to write to a read only bit in COMP will be ignored.