Layout is critical for good power-supply design. Layout example shows the recommended PCB-layout configuration.

A list of PCB layout considerations using the device is listed as follows:

• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid ground inner plane.
• PVIN-to-PGND decoupling capacitors are important for FET robustness. Besides the large volume 0603 or 0805 ceramic capacitors, TI highly recommends a 0.1µF 0402 ceramic capacitor with 25V / X7R rating on PVIN pin 20 (top layer) to bypass any high frequency current in PVIN to PGND loop. TI recommends the 25V rating, but the rating can be lowered to 16V rating for an application with tightly regulated 12V input bus.
• When one or more PVIN-to-PGND decoupling capacitors are placed on bottom layer, extra impedance is introduced to bypass IC PVIN node to IC PGND node. Placing at least 3 times PVIN vias on PVIN pad (formed by pin 20 to pin 24) and at least 9 times PGND vias on the thermal pad (underneath of the IC) is important to minimize the extra impedance for the bottom layer bypass capacitors.
• In addition to the PGND vias underneath the thermal pad, at least 4 PGND vias are required to be placed as close as possible to the PGND pin 7 to pin 10. At least 2 PGND vias are required to be placed as close as possible to the PGND pin 19. This action minimizes PGND bounces and also lowers thermal resistance.
• Place the VDRV-to-PGND decoupling capacitor as close as possible to the device. TI recommends a 2.2µF/6.3V/X7R/0603 or 4.7µF/6.3V/X6S/0603 ceramic capacitor. The voltage rating of this bypass capacitor must be at least 6.3V but no more than 10V to lower ESR and ESL. The recommended capacitor size is 0603 to minimize the capacitance drop due to DC bias effect. Make sure the VDRV to PGND decoupling loop is the smallest and make sure the routing trace is wide enough to lower impedance.
• Place the VCC-to-AGND decoupling capacitor on the same side and as close as possible to the IC. Connect VCC pin to VDRV pin with a 1ohm 0402 5% or better resistor. Placing a 1Ω resistor between the VCC pin and VDRV pin forms a RC filter on VCC pin, which greatly reduces the noise impact from power stage driver circuit. TI recommends a 2.2µF/6.3V/X7R/0603 or 4.7µF/6.3V/X6S/0603 ceramic capacitor. The voltage rating of this bypass capacitor must be at least 6.3V but no more than 10V to lower ESR and ESL.
• For remote sensing, the connections from the VOSNS/GOSNS pins to the remote location must be a pair of PCB traces with at least 12 mil trace width, and must implement Kelvin sensing across a high bypass capacitor of 0.1μF or higher. The ground connection of the remote sensing signal must be connected to GOSNS pin. The VOUT connection of the remote sensing signal must be connected to the VOSNS pin. To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any noise sources such as inductor and SW nodes, or high frequency clock lines. And TI recommends to shield the pair of remote sensing lines with ground planes above and below.
• For single-end sensing, connect the VOSNS pin to a high-frequency local bypass capacitor of 0.1μF or higher, and short GOSNS to AGND with shortest trace.
• The AGND must be connected to a solid PGND plane. TI recommends to place two AGND vias close to the pin to route AGND from top layer to bottom layer, and then connect the AGND trace to the PGND vias (underneath IC) through either a net-tie or a 0Ω resistor on the bottom layer.
• Connecting a resistor from PMB_ADDR pin to AGND sets the address. Do not to have any capacitor on this pin. A capacitor on the pin likely leads to a wrong detection result for address.
• Pin 6 (DNC) is a Do-Not-Connect pin. Do not connect pin 6 to any other net including ground.
• When device is configured with an external voltage divider, the high side resistor connects from VOSNS to VSEL/FB pins and the low side feedback resistor connects to VSEL/FB to GOSNS pins near the device.
• The return for the MSEL1 resistor, MSEL2 resistor, PMB_ADDR resistor and VSEL/FB resistor (when using internal feedback divider) is the quiet AGND island.