JAJSQT1 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address: | 7Eh |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Back-up: | No |
| Updates: | On-the-fly |
The STATUS_OTHER command returns one data byte containing PMBus First to Alert status. First to Alert does not assert SMB_ALERT on its own. It is informational only – regarding the state of SMB_ALERT if/when the device asserts SMB_ALERT by means of any other fault condition.
All supported bits may be cleared either by CLEAR_FAULTS, turning on the output through the mechanism programmed into ON_OFF_CONFIG, or individually by writing 1b to the STATUS_OTHER register in their position, per the PMBus 1.3.1 Part II specification section 10.2.3.
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | RW1C |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | FRST_2_ALRT |
| LEGEND: R/W1C = Read/Write 1 to clear; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:1 | Not supported | R | 0000000b | Not supported and always set to 0. |
| 0 | FRST_2_ALRT | RW1C | 0b | 0b: Latched flag indicating that the device has not asserted SMBALERT or SMBALERT
was asserted low before this device asserted SMBALERT. 1b: Latched flag indicating that the device has asserted SMBALERT and SMBALERT was not asserted low before this device asserted SMBALERT. |
The corresponding bit STATUS_BYTE is an OR’ing of the supported bits in this command. When any of the events in this command occurs and the bit representative of the events is set, the corresponding bit in STATUS_BYTE is updated. Likewise, if this byte is individually cleared (for example, by a write of 1b to a latched condition), it will clear the corresponding bit in STATUS_BYTE.