JAJSQT1 July 2024 TPS546E25
ADVANCE INFORMATION
CMD Address | 46h |
Write Transaction: | Write Word |
Read Transaction: | Read Word |
Format: | LINEAR11 |
Phased: | Yes |
NVM Backup: | EEPROM |
Updates: | On-the-fly |
The IOUT_OC_WARN_LIMIT command sets the average value of the output current that causes the overcurrent detector to indicate an overcurrent warn condition.
Return to Supported PMBus Commands.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R | R | R | R | R | R | R | R |
EXPONENT | IOUT_OC_WARN_LIMIT | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R | R | RW | RW | RW | RW | RW | RW |
IOUT_OC_WARN_LIMIT |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
15:11 | EXPONENT | R | 00000b | Linear format
two’s complement exponent. The exponent is
configured automatically through other settings,
with a result of 0b: 1A LSB |
10:6 | Reserved | R | 00000b | Not used and always set to 0. |
5:0 | IOUT_OC_WARN_LIMIT | R/W | NVM | These bits select the average IOUT warning threshold. |
Every mantissa binary value in the writable bits is writeable and readable. However, the actual divider is set to the nearest supported value. Additionally, that mantissa value restored from EEPROM is fixed for each setting supported in hardware.
Attempts to change the read-only bits (IOUT_OC_WARN_LIMIT[15:6]) will be considered invalid/unsupported data. The device will NACK the unsupported data and the received value will be ignored. The ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the (7Eh) STATUS_CML registers will be set.
IOUT_OC_WARN_LIMIT [5:0] | IOUT_OCW (A) | |
---|---|---|
Greater than or equal to | Less than | |
8d | 5 | |
8d | 13d | 10 |
13d | 18d | 15 |
18d | 23d | 20 |
23d | 28d | 25 |
28d | 33d | 30 |
33d | 38d | 35 |
38d | 43d | 40 |
43d | 48d | 45 |
48d | 53d | 50 |
53d | 55 |
When the PMBus host attempts to execute a P2+ write to IOUT_OC_WARN_LIMIT with the PHASE data in the command set to FFh, the expectation is to equally divide the commanded net “Stack OCW” level among the phases as their individual “Phase OCW” settings. In order to achieve that, the device does the following:
3-ph STACK OCW commanded[5:0] | PHASE IOUT_OC (A) | |
---|---|---|
Greater than or equal to | Less than | |
23d | 5 | |
33d | 38d | 10 |
41d | 53d | 15 |
51d | 68d | 20 |
60d | 83d | 25 |
68d | 98d | 30 |
78d | 113d | 35 |
87d | 128d | 40 |
93d | 143d | 45 |
101d | 158d | 50 |
111d | 159d | 55 |
When the PMBus host attempts to execute a P2+ read on IOUT_OC_WARN_LIMIT with the PHASE data in the command set to FFh, only the primary device will respond to P2+ read commands with incoming data for PHASE=FFh. The primary device multiplies the IOUT_OCW level by the STACK_NUMBER and reports the product back on the PMBus. For example, if the IOUT_OCW is 25A for the primary phase in a 3-phase rail, then a P2+ read with PHASE=FFh will yield 25 x 3 = 75A as the read-back value.