TPS54824は完全な機能を持つ17V、8Aの同期整流降圧型コンバータで、3.5mm×3.5mmの HotRod™ QFNパッケージで供給されます。
小型化を追求するため、効率を高めるとともに、ハイサイドMOSFETとローサイドMOSFETを統合しました。ピーク電流モード制御による部品数の削減と、高いスイッチング周波数によるインダクタの占有面積削減により、さらに容積が節約されています。
ピーク電流モード制御によりループ補償が簡素化され、過渡応答が高速です。過負荷状態の保護のため、ハイサイドおよびローサイドのソース電流に、サイクルごとのピーク電流制限が使用されます。ヒカップ機能は、短絡または過負荷障害が発生した場合に、MOSFETの電力損失を制限します。
パワーグッド・スーパーバイザ回路は、レギュレータの出力をモニタします。PGOODピンは、オープン・ドレイン出力で、出力電圧が安定化されているときハイ・インピーダンスになります。内部デグリッチ時間があるため、PGOODピンは障害が発生しない限り"L"になりません。
専用のENピンを使用して、レギュレータをオン/オフし、入力低電圧誤動作防止を調整できます。出力電圧のスタートアップ・ランプはSS/TRKピンにより制御されるため、スタンドアロンの電源として、あるいはトラッキング状況でも動作できます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
TPS54824 | RNV (18) | 3.50mm×3.50mm |
Changes from * Revision (November 2016) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BOOT | 1 | I | Floating supply voltage for high-side MOSFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between BOOT and SW pins. |
VIN | 2, 11 | I | Input voltage supply pin. Power for the internal circuit and the connection to drain of high-side MOSFET. Connect both pins to the input power source with a low impedance connection. Connect both pins and their neighboring PGND pins. |
PGND | 3, 4, 5, 8, 9, 10 | – | Ground return for low-side power MOSFET and its drivers. |
SW | 6, 7 | O | Switching node. Connected to the source of the high-side MOSFET and drain of the low-side MOSFET. |
AGND | 12 | – | Ground of internal analog circuitry. AGND must be connected to the PGND plane. |
RT/CLK | 13 | I | Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching frequency. In CLK mode, the device synchronizes to an external clock input to this pin. |
FB | 14 | I | Converter feedback input. Connect to the output voltage with a resistor divider. |
COMP | 15 | I | Error amplifier output and input to the PWM modulator. Connect loop compensation to this pin. |
SS/TRK | 16 | I | Soft-start and tracking pin. Connecting an external capacitor sets the soft-start time. This pin can also be used for tracking and sequencing. |
EN | 17 | I | Enable pin. Float or pull high to enable the device. Connect a resistor divider to this pin to implement adjustable under voltage lockout and hysteresis. |
PGOOD | 18 | O | Open-drain power good indicator. It is asserted low if output voltage is outside if the PGOOD thresholds, VIN is low, EN is low, device is in thermal shutdown or device is in soft-start. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | VIN | –0.3 | 19 | V |
BOOT | –0.3 | 27 | ||
BOOT (10 ns transient) | –0.3 | 30 | ||
BOOT (vs SW) | –0.3 | 7 | ||
SW | –1 | 20 | ||
SW (10 ns transient) | –3 | 23 | ||
EN, SS/TRK, PGOOD, RT/CLK, FB, COMP | –0.3 | 6.5 | ||
Operating Junction Temperature Range, TJ | -40 | 150 | °C | |
Storage Temperature Range, TSTG | -55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
Parameter | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|
VIN | Input voltage range | 4.5 | 17 | V | |
VOUT | Output Voltage | 0.6 | 12 | V | |
IOUT | Output current | 8 | A | ||
TJ | Operating junction temperature | -40 | 150 | °C | |
fSW | Switching Frequency (RT mode and PLL mode) | 200 | 1600 | kHz |
THERMAL METRIC(1) | TPS54824 | UNIT | |
---|---|---|---|
RNV | |||
18 PINS | |||
ThetaJA | Junction-to-ambient thermal resistance JEDEC | 57.1 | °C/W |
ThetaJA | Junction-to-ambient thermal resistance EVM | 34 | °C/W |
ThetaJCtop | Junction-to-case (top) thermal resistance | 26.3 | °C/W |
ThetaJB | Junction-to-board thermal resistance | 18.8 | °C/W |
PsiJT | Junction-to-top characterization parameter | 0.8 | °C/W |
PsiJB | Junction-to-board characterization parameter | 18.8 | °C/W |
ThetaJCbot | Junction-to-case (bottom) thermal resistance | 1.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT VOLTAGE | ||||||
UVLO_rise | VIN under-voltage lockout | V(VIN) rising | 4.1 | 4.3 | V | |
UVLO_fall | V(VIN) falling | 3.7 | 3.9 | V | ||
UVLO_hys | Hysteresis VIN voltage | 0.2 | V | |||
Ivin | Operating non-switching supply current | V(EN) = 5 V, V(FB) = 1.5 V | 580 | 800 | µA | |
Ivin_sdn | Shutdown supply current | V(EN) = 0 V | 3 | 11 | µA | |
ENABLE | ||||||
Ven_rise | EN threshold | V(EN) rising | 1.20 | 1.26 | V | |
Ven_fall | V(EN) falling | 1.1 | 1.15 | V | ||
Ven_hys | EN pin threshold voltage hysteresis | 50 | mV | |||
Ip | EN pin sourcing current | V(EN) = 1.1V | 1.2 | µA | ||
Iph | EN pin sourcing current | V(EN) = 1.3V | 4.8 | µA | ||
Ih | EN pin hysteresis current | 3.6 | µA | |||
FB | ||||||
VFB | Regulated FB voltage | TJ = 25°C | 596 | 600 | 604 | mV |
595 | 600 | 605 | mV | |||
ERROR AMPLIFIER | ||||||
gmea | Error Amplifier Transconductance (gm) | –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V | 1100 | µA/V | ||
Error Amplifier DC gain | 80 | dB | ||||
Icomp_src | Error Amplifier source current | V(FB) = 0 V | 100 | µA | ||
Icomp_snk | Error Amplifier sink current | V(FB) = 2 V | -100 | µA | ||
gmps | Power Stage Transconductance | 16 | A/V | |||
SOFT-START | ||||||
Iss | Soft-start current | 5 | µA | |||
V(SS/TRK) to V(FB) matching | V(SS/TRK) = 0.4 V | 25 | mV | |||
MOSFET | ||||||
Rds(on)_h | High-side switch resistance | TA = 25°C, V(VIN) = 12 V | 14.1 | mΩ | ||
TA = 25°C, V(VIN) = 4.5 V, V(BOOT-SW) = 4.5 V | 15.9 | mΩ | ||||
Rds(on)_l | Low-side switch resistance | TA = 25°C, V(VIN) = 12 V | 6.1 | mΩ | ||
TA = 25°C, V(VIN) = 4.5 V | 6.9 | mΩ | ||||
BOOT UVLO Falling | 2.2 | 2.6 | V | |||
CURRENT LIMIT | ||||||
Ioc_HS_pk | High-side peak current limit | 10.8 | 12.9 | 15 | A | |
Ioc_LS_snk | Low-side sinking current limit | –3.4 | A | |||
Ioc_LS_src | Low-side sourcing current limit | 9.3 | 11.4 | 13.6 | A | |
RT/CLK | ||||||
VIH | Logic high input voltage | 2 | V | |||
VIL | Logic low input voltage | 0.8 | V | |||
PGOOD | ||||||
Power good threshold | V(FB) rising (fault) | 108% | ||||
V(FB) falling (good) | 106% | |||||
V(FB) rising (good) | 91% | |||||
V(FB) falling (fault) | 89% | |||||
Ipg_lkg | Leakage current when pulled high | V(PGOOD) = 5 V | 5 | nA | ||
Vpg_low | PGOOD voltage when pulled low | I(PGOOD) = 2 mA | 0.3 | V | ||
Minimum VIN for valid output | V(PGOOD) < 0.5 V, I(PGOOD) = 4 mA | 0.7 | 1 | V | ||
Thermal protection | ||||||
TTRIP | Thermal protection trip point | Temperature Rising | 170 | °C | ||
THYST | Thermal protection hysteresis | 15 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
EN | ||||||
EN to start of switching | 135 | µs | ||||
PGOOD | ||||||
Deglitch time PGOOD going high | 272 | Cycles | ||||
Deglitch time PGOOD going low | 16 | Cycles | ||||
SW | ||||||
ton_min | Minimum on time | Measured at 50% to 50% of VIN, L = 0.68 µH, IOUT = 0.1 A | 95 | ns | ||
toff_min | Minimum off time (1) | V(BOOT-SW) ≥ 2.6 V | 0 | ns | ||
RT/CLK | ||||||
fsw_min | Minimum switching frequency (RT mode) | R(RT/CLK) = 250 kΩ | 200 | kHz | ||
Switching frequency (RT mode) | R(RT/CLK) = 100 kΩ | 450 | 500 | 550 | kHz | |
fsw_max | Maximum switching frequency (RT mode) | R(RT/CLK) = 30.1 kΩ | 1.6 | MHz | ||
fsw_clk | Switching frequency synchronization range (PLL mode) | 200 | 1600 | kHz | ||
RT/CLK falling edge to SW rising edge delay (PLL mode) | Measure at 500kHz with RT resistor in series with RT/CLK | 70 | ns | |||
HICCUP | ||||||
Wait time before hiccup | 512 | Cycles | ||||
Hiccup time before restart | 16384 | Cycles |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
RT/CLK | ||||||
Minimum synchronization signal pulse width (PLL mode) | 35 | ns |
V(EN) = 0.4 V |
V(SS/TRK) = 0.4 V |
V(FB) = 0.6 V | V(PGOOD) = 5 V |
R(RT/CLK) = 100 kΩ |
V(EN) = 5 V | V(FB) = 0.8 V |
VIN = 12 V | L = 0.68 µH |
R(RT/CLK) = 30.1 kΩ |