JAJSSB2 September   2024 TPS548B23

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 7.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 7.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 7.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 7.3.4  Enable
      5. 7.3.5  Soft Start
      6. 7.3.6  Power Good
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Remote Sense
      9. 7.3.9  Low-side MOSFET Zero-Crossing
      10. 7.3.10 Current Sense and Positive Overcurrent Protection
      11. 7.3.11 Low-side MOSFET Negative Current Limit
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting Point
        2. 8.2.2.2 Choose the Switching Frequency
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Choose the Input Capacitors (CIN)
        6. 8.2.2.6 VCC Bypass Capacitor
        7. 8.2.2.7 BOOT Capacitor
        8. 8.2.2.8 PG Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • VAN|19
サーマルパッド・メカニカル・データ
発注情報

7.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)

When the device is configured for internal feedback operation with the CFG 3-5 pins (See Table 7-3), the switching frequency and current limit are programmed by tying the CFG1-2 pins either high (VCC), low (GND) or left floating based on the table below:

Note: When the device is configured for internal feedback operation, the soft start time is set to 2ms, and the fault recovery is configured for hiccup.
Table 7-1 CFG 1-2 Pin Selection (Internal Feedback Configuration)
CFG1 VALLEY OCP (A) CFG2 SWITCHING FREQUENCY
(fSW) (kHz)(1)
VCC 21 VCC 600
GND 18 GND 800
Float 15 Float 1200
(1) Switching frequency is based on 3.3V output voltage. Frequency varies with output voltage.