SLVSHN0 September   2024 TPS548B23

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 7.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 7.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 7.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 7.3.4  Enable
      5. 7.3.5  Soft Start
      6. 7.3.6  Power Good
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Remote Sense
      9. 7.3.9  Low-side MOSFET Zero-Crossing
      10. 7.3.10 Current Sense and Positive Overcurrent Protection
      11. 7.3.11 Low-side MOSFET Negative Current Limit
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting Point
        2. 8.2.2.2 Choose the Switching Frequency
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Choose the Input Capacitors (CIN)
        6. 8.2.2.6 VCC Bypass Capacitor
        7. 8.2.2.7 BOOT Capacitor
        8. 8.2.2.8 PG Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

8.2.2.2 Choose the Switching Frequency

For this design we use the internal feedback mode and the switching frequency is configured by tying the CFG2 pin to VCC (600kHz), GND (800kHz), or by leaving it floating (1.2MHz). Refer to Table 7-3.

If the external feedback configuration is being used, the CFG1 pin is used to select between four switching frequencies (600kHz, 800kHz, 1MHz, or 1.2MHz) Refer to Table 7-2 for more information using the CFG1 pin configuration in external feedback mode.

Switching frequency selection is a tradeoff between higher efficiency and smaller system design size. Lower switching frequency yields higher overall efficiency but relatively bigger external components. Higher switching frequencies cause additional switching losses which impact efficiency and thermal performance. For this design, connect CFG2 pin to AGND to set the switching frequency to 800kHz

When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must be considered. Equation 6 calculates the maximum fSW before being limited by the minimum on-time. When hitting the minimum on-time limits of a converter with D-CAP4 control, the effective switching frequency changes to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a worst case estimation.

Equation 6. f S W m a x = V O U T V I N m a x × 1 t O N _ M I N ( m a x ) = 3.3   V 16   V × 1 25   n s = 8250   k H z

Equation 6 calculates the maximum fSW before being limited by the minimum off-time. When hitting the minimum off-time limits of a converter with D-CAP4 control, the operating duty cycle maxes out and the output voltage begins to drop with the input voltage. This equation requires the DC resistance of the inductor, RDCR, selected in the following step so this preliminary calculation assumes a resistance of 1.4mΩ. If operating near the maximum fSW limited by the minimum off-time, the variation in resistance across temperature must be considered when using Equation 8. The selected fSW of 800kHz is below the two calculated maximum values.

Equation 7. f S W m a x = V I N m i n - V O U T - I O U T m a x × R D C R + R D S O N _ H S t O F F _ M I N m a x × V I N m i n - I O U T m a x × R D S O N _ H S - R D S O N _ L S
Equation 8. f S W m a x = 8   V - 3.3   V - 20   A × 1.4   m Ω + 9.5   m Ω 150   n s × 8   V - 20   A × 9.5   m Ω - 3.3   m Ω = 3.8   M H z