JAJSKQ0A December   2020  – December 2022 TPS548B28

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3™ Control Mode
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode™ Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a 3.3-V Bus
      5. 7.4.5 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance On TI EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.5 Choose the Output Capacitor

There are three considerations for selecting the value of the output capacitor:

  1. Stability
  2. Steady state output voltage ripple
  3. Regulator transient response to a change load current
First, the minimum output capacitance must be calculated based on these three requirements. Equation 18 calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW to meet stability requirements. This requirement helps keep the LC double pole close to the internal zero. Equation 19 calculates the minimum capacitance to meet the steady state output voltage ripple requirement of 10 mV. This calculation is for CCM operation and does not include the portion of the output voltage ripple caused by the ESR or ESL of the output capacitors.

Equation 18. GUID-20201202-CA0I-XLMC-P739-HPQH7XSFFCQK-low.gif
Equation 19. GUID-20201202-CA0I-SPSG-H1GN-5WDFRXMK6TC1-low.gif

Equation 20 and Equation 21 calculate the minimum capacitance to meet the transient response requirement of 50 mV with a 10-A step. These equations calculate the necessary output capacitance to hold the output voltage steady while the inductor current ramps up or ramps down after a load step.

Equation 20. GUID-20201202-CA0I-NR2G-ZH1W-NN7XGXLFBX1J-low.gif
Equation 21. GUID-20201202-CA0I-M38C-9N29-SQQSJZ8XNLKP-low.gif

The output capacitance needed to meet the overshoot requirement is the highest value so this sets the required minimum output capacitance for this example. Stability requirements can also limit the maximum output capacitance and Equation 22 calculates the recommended maximum output capacitance. This calculation keeps the LC double pole above 1/100th the fSW. It can be possible to use more output capacitance but the stability must be checked through a bode plot or transient response measurement. The selected output capacitance is 8 x 47-µF 6.3-V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC bias effects. The selected capacitors derate to 85% their nominal value giving an effective total capacitance of 320 μF. This effective capacitance meets the minimum and maximum requirements.

Equation 22. GUID-20201202-CA0I-2GQ7-KZRN-TXPB7MPWL9PQ-low.gif

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If using non-ceramic capacitors, as a starting point, the ESR must be below the values calculated in Equation 23 to meet the ripple requirement and Equation 24 to meet the transient requirement. For more accurate calculations or if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the ripple and transient requirements can be met.

Equation 23. GUID-20201202-CA0I-JSRK-T5BN-0J45TVPNW98V-low.gif
Equation 24. GUID-8CF3486D-C375-4904-965E-305E103D8872-low.gif