JAJSKQ0A December   2020  – December 2022 TPS548B28

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3™ Control Mode
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode™ Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a 3.3-V Bus
      5. 7.4.5 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance On TI EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY
IQ(VIN)VIN quiescent currentVIN = 12 V, VEN = 2 V, VFB = VINTREF + 50mV (non-switching), no external bias on VCC pin9101007µA
ISD(VIN)VIN shutdown supply currentVIN = 12 V, VEN = 0 V, no external bias on VCC pin9.520µA
IQ(VCC)VCC quiescent currentTJ = 25°C, VIN = 12 V, VEN = 2 V, VFB = VINTREF + 50mV (non-switching), 3.3 V external bias on VCC pin680820µA
ISD(VCC)VCC shutdown currentVEN = 0 V, VIN = 0 V, 3.3 V external bias on VCC pin 4060µA
UVLO
VINUVLO(rise)VIN UVLO rising thresholdVIN rising, VCC = 3.3 V external bias2.12.42.7V
VINUVLO(fall)VIN UVLO falling thresholdVIN falling, VCC = 3.3 V external bias1.551.852.15V
ENABLE
VEN(rise)EN voltage rising thresholdEN rising, enable switching1.171.221.27V
VEN(fall)EN voltage falling thresholdEN falling, disable switching0.971.021.07V
VEN(hyst)EN voltage hysteresis0.2V
VEN(LKG)Input leakage current into EN pinVEN = 3.3 V0.55µA
EN internal pull-down resistanceEN pin to AGND. EN floating disables the converter.6500kΩ
INTERNAL LDO (VCC PIN)
Internal LDO output voltageVIN = 12 V, IVCC(Load) = 2 mA2.903.023.12V
VCCUVLO(rise)VCC UVLO rising thresholdVCC rising2.802.872.94V
VCCUVLO(fall)VCC UVLO falling thresholdVCC falling2.622.702.77
VCCUVLO(hys)VCC UVLO hysteresis0.17V
VCC LDO dropout voltage, 20mA loadTJ = 25°C, VIN = 4.0 V, IVCC(Load) = 20 mA, non-switching1.037V
VCC LDO short-circuit current limitVIN = 12 V, all temperature52105158mA
FB Threshold to turn off VCC LDOVCC LDO turn-off is controlled by FB voltage during EN shutdown event90146mV
REFERENCE VOLTAGE
VINTREFInternal voltage referenceTJ = 25°C600mV
Internal voltage reference rangeTJ = 0°C to 85°C597603mV
Internal voltage reference rangeTJ = –40°C to 125°C594606mV
IFB(LKG)Input leakage current into FB pinVFB = VINTREF140nA
SS/REFIN-to-FB AccuracyTJ = -40°C to 125°C, VSS/REFIN = 0.6 V, VSNS- = AGND, refer to VINTREF–0.6%0.6%
PSEUDO REMOTE SENSE
SS/REFIN-to-FB AccuracyTJ = -40°C to 125°C, VSS/REFIN = 0.6 V, VSNS- = AGND, refer to VINTREF–3.63.6mV
SWITCHING FREQUENCY
fSWSW switching frequency, FCCM operationTJ = 25°C, VIN = 12 V, VOUT=1.25V, RMODE = 0 Ω to AGND0.50.60.7MHz
TJ = 25°C, VIN = 12 V, VOUT=1.25V, RMODE = 30.1 kΩ to AGND0.60.70.8
TJ = 25°C, VIN = 12 V, VOUT=1.25V, RMODE = 60.4 kΩ to AGND0.700.85(3)1.0
STARTUP
EN to first switching delay, internal LDOThe delay from EN goes high to the first SW rising edge with internal LDO configuration. CVCC = 2.2 µF. CSS/REFIN = 220 nF.0.932ms
EN to first switching delay, external VCC biasThe delay from EN goes high to the first SW rising edge with external VCC bias configuration. VCC bias should reach regulation before EN ramp up. CSS/REFIN = 220 nF.0.550.9ms
tSSInternal fixed Soft-start timeVO rising from 0 V to 95% of final setpoint, CSS/REFIN = 1nF11.5ms
SS/REFIN sourcing currentVSS/REFIN = 0 V36µA
SS/REFIN sinking currentVSS/REFIN = 1 V12µA
POWER STAGE
RDSON(HS)High-side MOSFET on-resistanceTJ = 25°C, BOOT–SW = 3 V7.7mΩ
RDSON(LS)Low-side MOSFET on-resistanceTJ = 25°C, VCC = 3 V2.4mΩ
tON(min)Minimum on-timeTJ = 25°C, VCC = Internal LDO7085ns
tOFF(min)Minimum off-timeTJ = 25°C, VCC = Internal LDO, HS FET Gate falling to rising220ns
BOOT CIRCUIT
IBOOT(LKG)BOOT leakage currentTJ = 25°C, VBOOT-SW = 3.3 V3550µA
VBOOT-SW(UV_F)BOOT-SW UVLO falling thresholdTJ = 25°C, VIN = 12 V, VBOOT-SW falling2.0V
OVERCURRENT PROTECTION
RTRIPTRIP pin resistance range020kΩ
Current limit clampValley current on LS FET, 0-Ω ≤ RTRIP ≤ 5.24-kΩ19.222.925A
KOCLConstant for RTRIP equation120000A×Ω
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = AGND 19.2 22.9 25 A
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 5.23 kΩ 22.9 A
IOCL (valley)Current limit thresholdValley current on LS FET, RTRIP = 6.04 kΩ19.9A
IOCL (valley)Current limit thresholdValley current on LS FET, RTRIP = 7.5 kΩ16A
IOCL (valley)Current limit thresholdValley current on LS FET, RTRIP = 10 kΩ12A
IOCL (valley)Current limit thresholdValley current on LS FET, RTRIP = 14.7 kΩ8.2A
IOCL (valley)Current limit thresholdValley current on LS FET, RTRIP = 20 kΩ6A
KOCL Constant KOCL tolerance RTRIP = 5.23 kΩ -16.4% 9%
KOCLConstant KOCL tolerance6.04 kΩ ≤ RTRIP ≤ 10 kΩ-12%12%
KOCLConstant KOCL toleranceRTRIP = 14.7 kΩ-18%18%
KOCLConstant KOCL toleranceRTRIP = 20 kΩ-21%21%
INOCLNegative current limit thresholdAll VINs–12–10–8A
IZCZero-cross detection current threshold, open loopVIN = 12 V, VCC = Internal LDO400mA
OUTPUT OVP AND UVP
VOVPOutput Overvoltage-protection (OVP) threshold voltage113%116%119%
tOVP(delay)Output OVP response delayWith 100-mV overdrive400ns
VUVPOutput Undervoltage-protection (UVP) threshold voltage77%80%83%
tUVP(delay)Output UVP filter delay68µs
POWER GOOD
VPGTHPGOOD thresholdPGOOD high, FB rising89%92.5%95%
PGOOD low, FB rising113%116%119%
PGOOD low, FB falling77%80%83%
OOB (Out-Of-Bounds) thresholdPGOOD high, FB rising103%105.5%108%
IPGPGOOD sink currentVPGOOD = 0.4 V, VIN = 12 V, VCC = Internal LDO17mA
VPG(low)PGOOD low-level output voltageIPGOOD = 5.5 mA, VIN = 12 V, VCC = Internal LDO400mV
tPGDLY(rise)Delay for PGOOD from low to high1.061.33ms
tPGDLY(fall)Delay for PGOOD from high to low0.55µs
IPG(LKG)PGOOD leakage current when pulled highTJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF5µA
PGOOD clamp low-level output voltageVIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 100-kΩ resistor710850mV
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 10-kΩ resistor8501000mV
Min VCC for valid PGOOD outputVPGOOD ≤ 0.4 V1.5V
OUTPUT DISCHARGE
RDischgOutput discharge resistanceVIN = 12 V, VCC = Internal LDO, VSW = 0.5 V, power conversion disabled70Ω
THERMAL SHUTDOWN
TSDNThermal shutdown threshold(1)Temperature rising150165°C
THYSTThermal shutdown hysteresis(1)30°C
(1) Specified by design. Not production tested.
(2) Fsw variates with Vout due to D-CAP3 control mode.