JAJSKQ0A December 2020 – December 2022 TPS548B28
PRODUCTION DATA
When the device is disabled through EN, it enables the output voltage discharge mode. This mode forces both high-side and low-side FETs to latch off, but turns on the discharge FET, which is connected from SW to PGND, to discharge the output voltage. After the FB voltage drops below 90 mV, the discharge FET is turned off.
The output voltage discharge mode is activated by any of the following fault events: