JAJSQ82B November   2023  – July 2024 TPS548D26

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using an External Bias on the VCC and VDRV Pin
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Fixed VCC_OK UVLO
        2. 6.3.2.2 Fixed VDRV UVLO
        3. 6.3.2.3 Fixed PVIN UVLO
        4. 6.3.2.4 Enable
      3. 6.3.3  Set the Output Voltage
      4. 6.3.4  Differential Remote Sense and Feedback Divider
      5. 6.3.5  Start-Up and Shutdown
      6. 6.3.6  Loop Compensation
      7. 6.3.7  Set Switching Frequency and Operation Mode
      8. 6.3.8  Switching Node (SW)
      9. 6.3.9  Overcurrent Limit and Low-side Current Sense
      10. 6.3.10 Negative Overcurrent Limit
      11. 6.3.11 Zero-Crossing Detection
      12. 6.3.12 Input Overvoltage Protection
      13. 6.3.13 Output Undervoltage and Overvoltage Protection
      14. 6.3.14 Overtemperature Protection
      15. 6.3.15 Power Good
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 6.4.3 Powering the Device From a 12-V Bus
      4. 6.4.4 Powering the Device From a Split-Rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Inductor Selection
        2. 7.2.3.2 Input Capacitor Selection
        3. 7.2.3.3 Output Capacitor Selection
        4. 7.2.3.4 VCC and VRDV Bypass Capacitor
        5. 7.2.3.5 BOOT Capacitor Selection
        6. 7.2.3.6 PG Pullup Resistor Selection
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance on TPS548D26 Evaluation Board
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

TPS548D26 RXX 37-Pin WQFN-FCRLF Package (Top View)Figure 4-1 RXX 37-Pin WQFN-FCRLF Package
(Top View)
TPS548D26 RXX 37-Pin WQFN-FCRLF Package (Bottom View)Figure 4-2 RXX 37-Pin WQFN-FCRLF Package (Bottom View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
AGND32GGround pin, reference point for internal control circuitry
AVIN3PSupply rail for the internal VCC LDO. Connect a 1-μF, 25-V ceramic capacitor to AGND to bypass this pin.
BOOT26PSupply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to PHASE pin. TI recommends a high temperature (X7R) 0.1 μF or greater value ceramic capacitor.
DNC6—Do Not Connect (DNC) pin. This pin is the output of internal circuitry and must be floating. Pin 6 and pin 37 can be shorted together but NO any other PCB connection is allowed on pin 6.
EN27IEnable pin, an active-high input pin that, when asserted high, causes the converter to begin the soft-start sequence for the output voltage rail. When de-asserted low, the converter de-asserts PG pin and begins the shutdown sequence of the output voltage rail and continue to completion.
FB30IPositive input of the differential remote sense amplifier, connect to the center point of an external voltage divider. The voltage divider must be connected to output remote sense point.
GOSNS31INegative input of the differential remote sense circuit, connect to the ground sense point on the load side.
ILIM1IOvercurrent limit selection pin. Connect a resistor to AGND to select the overcurrent limit threshold.
MODE36IThe MODE pin selects the switching frequency and sets the operation mode to FCCM or DCM, by connecting a resistor to AGND.
SS29IThe SS pin selects the soft-start time, internal compensation and the fault response, by connecting a resistor to AGND.
NC33, 34, 35—No connection (NC) pin. There is no active circuit connected inside the IC. These pins can be connected to ground plane or left open.
NC37—No connection (NC) pin. This pin is floating internally. Pin 37 and pin 6 can be shorted together.
PG2OPower-good output signal. The PG indicator is asserted when the output voltage reaches the regulation. The PG indicator de-asserts low when the EN pin is pulled low or a shutdown fault occurs. This open-drain output requires an external pullup resistor.
PGND7 – 10, 19GPower ground for the internal power stage.
PHASE25—Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap capacitor from BOOT pin to this pin.
PVIN20 – 24PPower input for both the power stage. PVIN is the input of the internal VCC LDO as well.
SW11 – 18OOutput switching terminal of the power converter. Connect these pins to the output inductor.
VCC4PInternal VCC LDO output and also the input for the internal control circuitry. A 2.2-μF (or 1 μF), at least 6.3-V rating ceramic capacitor is required to be placed from VCC pin to AGND for decoupling.
VDRV5PPower supply input for gate driver circuit. A 2.2-μF (or 4.7 μF), at least 6.3-V rating ceramic capacitor is required to be placed from VDRV pin to PGND pins to decouple the noise generated by driver circuitry. An external 5-V bias can be connected to this pin to save the power losses on the internal LDO.
VOSNS28IOutput voltage sense point for internal on-time generation circuitry. Ti recommends shorting this pin directly to the VOUT sense point. Adding any resistance higher than 51 Ω between VOUT sense point and the VOSNS pin shifts switching frequency higher than the desired setting. Contact Texas Instruments if a resistor has to be placed between the VOUT sense point and the VOSNS pin.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.