JAJSDE0A
June 2017 – February 2024
TPS549B22
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
25-A FET
6.3.2
On-Resistance
6.3.3
Package Size, Efficiency and Thermal Performance
6.3.4
Soft-Start Operation
6.3.5
VDD Supply Undervoltage Lockout (UVLO) Protection
6.3.6
EN_UVLO Pin Functionality
6.3.7
Fault Protections
6.3.7.1
Current Limit (ILIM) Functionality
6.3.7.2
VDD Undervoltage Lockout (UVLO)
6.3.7.3
Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
6.3.7.4
Out-of-Bounds Operation
6.3.7.5
Overtemperature Protection
6.4
Device Functional Modes
6.4.1
D-CAP3™ Control Mode Topology
6.4.2
DCAP Control Topology
6.5
Programming
6.5.1
Programmable Pin-Strap Settings
6.5.1.1
Address Selection (ADDR) Pin
6.5.1.2
VSEL Pin
6.5.1.3
D-CAP3™ Control Mode Selection
6.5.1.4
Application Workaround to Support 4-ms and 8-ms SS Settings
6.5.2
Programmable Analog Configurations
6.5.2.1
RSP/RSN Remote Sensing Functionality
6.5.2.1.1
Output Differential Remote Sensing Amplifier
6.5.2.2
Power Good (PGOOD Pin) Functionality
6.5.3
PMBus Programming
6.5.3.1
TPS549B22 Limitations to the PMBUS Specifications
6.5.3.2
Target Address Assignment
6.5.3.3
PMBUS Address Selection
6.5.3.4
Supported Formats
6.5.3.4.1
Direct Format — Write
6.5.3.4.2
Combined Format — Read
6.5.3.5
Stop Separated Reads
6.5.3.6
Supported PMBUS Commands and Registers
7
Register Maps
7.1
OPERATION Register (address = 1h)
7.2
ON_OFF_CONFIG Register (address = 2h)
7.3
CLEAR FAULTS (address = 3h)
7.4
WRITE PROTECT (address = 10h)
7.5
STORE_DEFAULT_ALL (address = 11h)
7.6
RESTORE_DEFAULT_ALL (address = 12h)
7.7
CAPABILITY (address = 19h)
7.8
VOUT_MODE (address = 20h)
7.9
VOUT_COMMAND (address = 21h)
7.10
VOUT_MARGIN_HIGH (address = 25h) ®
7.11
VOUT_MARGIN_LOW (address = 26h)
7.12
STATUS_BYTE (address = 78h)
7.13
STATUS_WORD (High Byte) (address = 79h)
7.14
STATUS_VOUT (address = 7Ah)
7.15
STATUS_IOUT (address = 7Bh)
7.16
STATUS_CML (address = 7Eh)
7.17
MFR_SPECIFIC_00 (address = D0h)
7.18
MFR_SPECIFIC_01 (address = D1h)
7.19
MFR_SPECIFIC_02 (address = D2h)
7.20
MFR_SPECIFIC_03 (address = D3h)
7.21
MFR_SPECIFIC_04 (address = D4h)
7.22
MFR_SPECIFIC_06 (address = D6h)
7.23
MFR_SPECIFIC_07 (address = D7h)
7.24
MFR_SPECIFIC_44 (address = FCh)
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
TPS549B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.3.1
Custom Design With WEBENCH® Tools
8.2.3.2
Switching Frequency Selection
8.2.3.3
Inductor Selection
8.2.3.4
Output Capacitor Selection
8.2.3.4.1
Minimum Output Capacitance to Make Sure of Stability
8.2.3.4.2
Response to a Load Transient
8.2.3.4.3
Output Voltage Ripple
8.2.3.5
Input Capacitor Selection
8.2.3.6
Bootstrap Capacitor Selection
8.2.3.7
BP Pin
8.2.3.8
R-C Snubber and VIN Pin High-Frequency Bypass
8.2.3.9
Optimize Reference Voltage (VSEL)
8.2.3.10
MODE Pin Selection
8.2.3.11
ADDR Pin Selection
8.2.3.12
Overcurrent Limit Design
8.2.4
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Examples
8.4.3
Mounting and Thermal Profile Recommendation
9
Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.1.1.1
Custom Design With WEBENCH® Tools
9.2
Documentation Support
9.2.1
Related Documentation
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RVF|40
サーマルパッド・メカニカル・データ
RVF|40
QFND333E
発注情報
jajsde0a_oa
jajsde0a_pm
6.2
Functional Block Diagram