JAJSOL2 August   2024 TPS55287

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  EXTVCC Power Supply
      3. 6.3.3  Operation Mode Setting
      4. 6.3.4  Input Undervoltage Lockout
      5. 6.3.5  Enable and Programmable UVLO
      6. 6.3.6  Soft Start
      7. 6.3.7  Shutdown and Load Discharge
      8. 6.3.8  Switching Frequency
      9. 6.3.9  Switching Frequency Dithering
      10. 6.3.10 Inductor Current Limit
      11. 6.3.11 Internal Charge Path
      12. 6.3.12 Output Voltage Setting
      13. 6.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 6.3.14 Output Current Limit
      15. 6.3.15 Overvoltage Protection
      16. 6.3.16 Output Short Circuit Protection
      17. 6.3.17 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
    5. 6.5 Programming
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 Target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multiread and Multiwrite
    6. 6.6 Register Maps
      1. 6.6.1 REF Register (Address = 0h, 1h)
      2. 6.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
      3. 6.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
      4. 6.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
      5. 6.6.5 CDC Register (Address = 5h) [reset = 11100000h]
      6. 6.6.6 MODE Register (Address = 6h) [reset = 00100000h]
      7. 6.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Switching Frequency
        2. 7.2.2.2 Output Voltage Setting
        3. 7.2.2.3 Inductor Selection
        4. 7.2.2.4 Input Capacitor
        5. 7.2.2.5 Output Capacitor
        6. 7.2.2.6 Output Current Limit
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.7 Loop Stability

The TPS55287 uses average current control scheme. The inner current loop uses internal compensation and requires the inductor value must be larger than 1.2/fSW. The outer voltage loop requires an external compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation network comprised of resistor and ceramic capacitors is connected to the COMP pin.

The TPS55287 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require loop compensations. The restrictive one of both compensations is selected as the overall compensation from a loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).

The power stage in boost mode can be modeled by Equation 18.

Equation 19. TPS55287

where

  • RLOAD is the output load resistance.
  • D is the switching duty cycle in boost mode.
  • RSENSE is the equivalent internal current sense resistor, which is 0.055 Ω.

The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use Equation 20 to Equation 22 to calculate them.

Equation 20. TPS55287
Equation 21. TPS55287
Equation 22. TPS55287

The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the control portion of the loop. The transfer function of the control portion is shown by Equation 23.

Equation 23. TPS55287

where

  • GEA is the transconductance of the error amplifier.
  • REA is the output resistance of the error amplifier.
  • VREF is the reference voltage input to the error amplifier.
  • VOUT is the output voltage.
  • fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network.
  • fCOMZ is the zero’s frequency of the compensation network.

The total open-loop gain is the product of GPS(s) and GC(s). The next step is to choose the loop crossover frequency, fC, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, fSW, or 1/5 of the RHPZ frequency, fRHPZ.

Then, set the value of RC, CC, and CP by Equation 24 to Equation 26.

Equation 24. TPS55287

where

  • fC is the selected crossover frequency.
Equation 25. TPS55287
Equation 26. TPS55287

If the calculated CP is less than 10 pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.