JAJSPI2A december   2022  – april 2023 TPS552892

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  EXTVCC Power Supply
      3. 7.3.3  Input Undervoltage Lockout
      4. 7.3.4  Enable and Programmable UVLO
      5. 7.3.5  Soft Start
      6. 7.3.6  Shutdown
      7. 7.3.7  Switching Frequency
      8. 7.3.8  Switching Frequency Dithering
      9. 7.3.9  Inductor Current Limit
      10. 7.3.10 Internal Charge Path
      11. 7.3.11 Output Voltage Setting
      12. 7.3.12 Output Current Monitoring and Cable Voltage Droop Compensation
      13. 7.3.13 Output Current Limit
      14. 7.3.14 Overvoltage Protection
      15. 7.3.15 Output Short Circuit Protection
      16. 7.3.16 Power Good
      17. 7.3.17 Constant Current Output Indication
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power Save Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 3.0 36 V
VVIN_UVLO Under voltage lockout threshold VIN rising 2.8 2.9 3.0 V
VIN falling 2.6 2.65 2.7 V
IQ Quiescent current into VIN pin IC enabled, no load, no switching. VIN = 3.0V to 24V, VOUT = 0.8V, VFB = VREF + 0.1V, RFSW=100kΩ, Tj up to 125°C 760 860 µA
Quiescent current into VOUT pin IC enabled, no load, no switching, VIN = 3.0V, VOUT = 3V to 20V, VFB = VREF + 0.1V, RFSW=100kΩ, Tj up to 125°C 760 860 µA
ISD Shutdown current into VIN pin IC disabled, VIN = 3.0V to 14V, Tj up to 125°C, EXTVCC pin floating 0.8 3 µA
VCC Internal regulator output IVCC = 50mA, VIN = 8V, VOUT = 20V 5.05 5.2 5.45 V
EN/UVLO
VEN_H EN Logic high threshold VCC = 3.0V to 5.5V 1.15 V
VEN_L EN Logic low threshold VCC = 3.0V to 5.5V 0.4 V
VEN_HYS Enable threshold hysteresis VCC = 3.0V to 5.5V 0.04 V
VUVLO UVLO rising threshold at the EN/UVLO pin VCC = 3.0V to 5.5V 1.20 1.23 1.26 V
VUVLO_HYS UVLO threshold hysteresis VCC = 3.0V to 5.5V 10 mV
IUVLO Sourcing current at the EN/UVLO pin VUVLO = 1.3V 4.4 5 5.6 µA
OUTPUT
VOUT Output voltage range 0.8 22 V
VOVP Output overvoltage protection threshold 22.5 23.5 24.5 V
VOVP_HYS Over voltage protection hysteresis 1 V
IFB_LKG Leakage current at FB pin Tj up to 125°C 100 nA
IVOUT_LKG Leakage current into VOUT pin IC disabled, VOUT = 20V, VSW2 = 0V, Tj up to 125°C 1 20 µA
REFERENCE VOLTAGE
VREF Reference voltage at the FB pin 1.188 1.2 1.212 V
POWER SWITCH
RDS(on) Low-side MOSFET on resistance on buck side VOUT = 20V, VCC=5.2V 22 mΩ
High-side MOSFET on resistance on buck side VOUT = 20V, VCC=5.2V 14 mΩ
Low-side MOSFET on resistance on boost side VOUT = 20V, VCC=5.2V 11 mΩ
High-side MOSFET on resistance on boost side VOUT = 20V, VCC=5.2V 11 mΩ
INTERNAL CLOCK
fSW Switching frequency RFSW =100k 180 200 220 kHz
RFSW =8.4k 2000 2200 2400 kHz
tOFF_min Min. off time Boost mode 90 145 ns
tON_min Min. on time Buck mode 90 130 ns
VFSW Voltage at FSW pin 1 V
CURRENT LIMIT
ILIM_AVG Average inductor current limit TPS552892, VIN = 8V, VOUT = 20V, FSW = 400kHz, VCC = 5.2V 7 8 9 A
ILIM_PK_H Peak inductor current limit at high side TPS552892, VIN = 8V, VOUT = 20V, FSW = 400kHz 13 A
ILIM_PK_L Peak inductor current limit at low side TPS552892, VIN = 8V, VOUT = 20V, FSW = 400kHz 12 A
VSNS Current loop regulation voltage between ISP and ISN pin 48 50 52 mV
CABLE VOLTAGE DROP COMPENSATION
VCDC Voltage at the CDC pin RCDC = 20kΩ or floating, VISP – VISN = 50mV 0.95 1 1.05 V
RCDC = 20kΩ or floating, VISP – VISN = 2mV 40 75 mV
IFB_CDC FB  pin sinking current External output feedback, RCDC = 20kΩ, VISP – VISN = 50mV 7.23 7.5 7.87 µA
External output feedback, RCDC = 20kΩ, VISP – VISN = 0mV 0 0.3 µA
External output feedback, RCDC = floating, VISP – VISN = 50mV 0 0.3 µA
ERROR AMPLIFIER
ISINK COMP pin sink current VFB = VREF + 400mV, VCOMP=1.5V, VCC=5V 20 µA
ISOURCE COMP pin source current VFB = VREF - 400mV, VCOMP=1.5V, VCC=5V 60 µA
VCCLPH High clamp voltage at the COMP pin FPWM mode, VOUT  = 1.8V to 22V 1.3 V
VCCLPL Low clamp voltage at the COMP pin FPWM mode 0.7 V
GEA Error amplifier transconductance 190 µA/V
SOFT START
tSS Soft-start time 2.5 3.6 5 ms
SPREAD SPECTRUM
IDITH_CHG Dithering charge current VDITH/SYNC = 1.0V; RFSW=49.9kΩ; voltage rising from 0.9V 2 µA
IDITH_DIS Dithering discharge current VDITH/SYNC = 1.0V; RFSW=49.9kΩ; voltage falling from 1.1V 2 µA
VDITH_H Dither high threshold 1.07 V
VDITH_L Dither low threshold 0.93 V
SYNCHRONOUS CLOCK
VSNYC_H Sync clock high voltage threshold 1.2 V
VSYNC_L Sync clock low voltage threshold 0.4 V
tSYNC_MIN Minimum sync clock pulse width 50 ns
HICCUP
tHICCUP Hiccup off time 76 ms
MODE  
VMODE MODE logic high  threshold VCC = 3V to 5.5V 1.2 V
VMODE MODE logic low  threshold VCC = 3V to 5.5V 0.4 V
EXTVCC
VEXTVCC EXTVCC Logic high threshold VCC = 3V to 5.5V 1.2 V
VEXTVCC EXTVCC Logic Low threshold VCC = 3V to 5.5V 0.4 V
Power Good
IPG_H Leakage current into PG pin when outputting high impedance VPG = 5V 100 nA
VPG_L Output low voltage range of the PG pin Sinking 4mA current 0.1 0.2 V
Current Limit Indication
ICC_H Leakage current into CC pin when outputting high impedance VCC = 5 V 100 nA
VCC_L Output low voltage range of the CC pin Sinking 4-mA current 0.1 0.2 V
PROTECTION
TSD Thermal shutdown threshold TJ rising 175 °C
TSD_HYS Thermal shutdown hysteresis TJ falling below Tsd 20 °C