The TPS56623x has overcurrent protection and undervoltage protection. The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain-to-source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by the following:

• V_IN
• V_OUT
• the on-time
• the output inductor value

During the on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I_OUT. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse. This is true even if the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of overcurrent protection. When the load current is higher than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and the current is limited. The output voltage tends to drop because the load demand is higher than what the converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator detects it and the device shuts off after a 256-μs wait time. The device then restarts after the hiccup time (typically 7 × T_ss). When the overcurrent condition is removed, the output is recovered.