JAJSJ68B May   2020  – December 2023 TPS566231 , TPS566238

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2 Soft Start
      3. 6.3.3 Power Good
      4. 6.3.4 Large Duty Operation
      5. 6.3.5 Overcurrent Protection and Undervoltage Protection
      6. 6.3.6 Overvoltage Protection
      7. 6.3.7 UVLO Protection
      8. 6.3.8 Output Voltage Discharge
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Advanced Eco-mode Control
      2. 6.4.2 Force CCM Mode
      3. 6.4.3 Standby Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design with WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Setpoint
        3. 7.2.2.3 Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design with WEBENCH® Tools
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.3 Power Good

The TPS566231P and TPS566238P have the PG pin as a power-good indicator. The PG pin is an open-drain output. After the VFB is between 90% and 110% of the internal reference voltage (VREF), the PG is de-asserted and floats after a 1-ms de-glitch time. TI recommends a 100-kΩ pullup resistor to pull the voltage up to VCC. The PG pin is pulled low when:

  • The FB pin voltage is lower than 85% or greater than 115% of the target output voltage
  • The device is in an OVP, UVP, or thermal shutdown event
  • Or during the soft-start period