SLVSCV3B March   2015  – June 2015 TPS566250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Operation
      2. 8.3.2 PWM Frequency and Adaptive On-Time Control
      3. 8.3.3 Soft Start and Pre-Biased Soft Start
      4. 8.3.4 Overcurrent Protection
      5. 8.3.5 UVLO Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Auto-Skip Eco-mode™ Control
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 I2C Protocol
        1. 8.5.2.1 Input Voltage
        2. 8.5.2.2 Output Voltage
        3. 8.5.2.3 Data Format
        4. 8.5.2.4 START and STOP Conditions
      3. 8.5.3 I2C Chip Address Byte
    6. 8.6 Register Maps
      1. 8.6.1 I2C Register Address Byte
        1. 8.6.1.1 Output Voltage Register (offset = 00000000) [reset = 0h]
        2. 8.6.1.2 Power Good State Register (offset = 00011000) [reset = 18h]
      2. 8.6.2 CheckSum Bit
      3. 8.6.3 Output Voltage Registers
      4. 8.6.4 Summary of Default Control Bits
        1. 8.6.4.1 DAC Settle
        2. 8.6.4.2 Operation During VID Transition
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Resistors Selection
        2. 9.2.2.2 Output Filter Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Bootstrap Capacitor Selection
      3. 9.2.3 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Third-Party Products Disclaimer
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Thermal Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The devices are synchronous step down DC-DC converters rated at different output currents whose output voltage can be dynamically scaled by sending commands over an I2C interface. This section discusses the design of the external components to complete the power supply design by using a typical application as a reference.

9.2 Typical Application

TPS566250 application_circuit_slvscv3.gifFigure 17. Typical Application Schematic

Table 4. Components

REFERENCE DESIGNATOR PART NUMBER MANUFACTURER
L1 744 314 150 Wurth Electronics
C6 , C7 C1210C226K9RACTU Kemet

9.2.1 Design Requirements

For this design example, use the parameters shown in Table 5.

Table 5. Design Example

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 12 V
Output voltage 1.1 V
Transient response, 0 A – 6 A load step ΔVOUT = ±5%
Output voltage ripple 25 mV
Input ripple voltage 400 mV
Output current rating 6 A
Operating Frequency 650 kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1% tolerance or better divider resistors. Use 1.37 kΩ for R1 and 1.65 kΩ for R2.

Equation 3. TPS566250 eq_2_slvscv3.gif

9.2.2.2 Output Filter Selection

The output filter used with the TPS566250 is an LC circuit. This LC filter has double pole at:

Equation 4. TPS566250 eq_3_slvscv3.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 6.

Table 6. Recommended Component Values

Output Voltage (V) R1 (kΩ) R2 (kΩ) C4 (pF)(1) L1 (µH) C67 (µF)
MIN TYP MAX MIN TYP MAX
1 1.37 1.65 1.5 22 - 68
1.1 (Default) 1.37 1.65 1.5 22 - 68
1.2 1.37 1.65 1.5 22 - 68
1.5 1.37 1.65 1.5 22 - 68
1.8 1.37 1.65 1.5 22 - 68
(1) Optional

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. For the calculations, use 500 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS current of Equation 7.

Equation 5. TPS566250 eq_4_slvscv3.gif
Equation 6. TPS566250 eq_5_slvscv3.gif
Equation 7. TPS566250 eq_6_slvscv3.gif

The capacitor value and ESR determines the amount of output voltage ripple. The TPS566250 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF.

9.2.2.3 Input Capacitor Selection

The TPS566250 requires an input decoupling capacitor and a bulk capacitor depending on the application. A ceramic capacitor of 10 µF or above is recommended for the decoupling capacitor. Additionally, a 0.1-µF ceramic capacitor from VIN to GND is also recommended to improve the stability and reduce the SW node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.

9.2.2.4 Bootstrap Capacitor Selection

The 0.1-µF ceramic capacitors must be connected between the BOOT to SW pins for proper operation. It is recommended to use ceramic capacitors with a dielectric of X5R or better.

9.2.3 Application Performance Curves

VIN = 12 V, VOUT = 1.1 V, TA = 25°C, unless otherwise specified.

TPS566250 D011_SLVSCV3.gif
VIN = 12 V
Figure 18. Efficiency vs Output Current
TPS566250 D016_SLVSCV3.gif
VOUT = 0.6 V
Figure 20. Efficiency vs Output Current
TPS566250 D012_SLVSCV3.gif
Figure 22. Load Regulation
TPS566250 wvfrm_01_load_trans_slvscv3.png
Figure 24. Load Transient
TPS566250 wvfrm_03_inpt_outpt_ccm_slvscv3.png
Figure 26. Continuous Conduction Mode
(Inductor Current)
TPS566250 wvfrm_05_inpt_outpt_psm_slvscv3.png
Figure 28. Skip Mode (Inductor Current)
TPS566250 wvfrm_07_pwrdwn_vin_slvscv3.png
Figure 30. Power Down VIN
TPS566250 wvfrm_09_en_pwrdwn_slvscv3.png
Figure 32. Power Down with EN
TPS566250 wvfrm_11_stp_up_w_vid_slvscv3.png
Figure 34. VOUT Step Up With VID
TPS566250 wvfrm_13_crrnt_lmt_12vin_slvscv3.png
Figure 36. Hiccup Current Limit
TPS566250 D015_SLVSCV3.gif
VOUT = 1.87 V
Figure 19. Efficiency vs Output Current
TPS566250 D017_SLVSCV3.gif
VOUT = 1.1 V
Figure 21. Efficiency vs Load Current
TPS566250 D013_SLVSCV3.gif
Figure 23. Line Regulation
TPS566250 wvfrm_02_line_stp_slvscv3.png
Figure 25. Line Transient
TPS566250 wvfrm_04_inpt_outpt_dcm_slvscv3.png
Figure 27. Discontinuous Conduction Mode
(Inductor Current)
TPS566250 wvfrm_06_startup_vin_slvscv3.png
Figure 29. Start Up With VIN
TPS566250 wvfrm_08_en_pwrup_slvscv3.png
Figure 31. Start Up With EN
TPS566250 wvfrm_10_prebias_pwrdwn_slvscv3.png
Figure 33. Start Up With EN and Prebias
TPS566250 wvfrm_12_stp_dwn_w_vid_slvscv3.png
Figure 35. VOUT Step Down With VID