JAJSCL3C October   2016  – August 2023 TPS568215

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation and D-CAP3 Control Mode
      2. 7.3.2  Eco-mode Control
      3. 7.3.3  4.7 V LDO and External Bias
      4. 7.3.4  MODE Selection
      5. 7.3.5  Soft Start and Pre-biased Soft Start
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Power Good
      8. 7.3.8  Overcurrent Protection and Undervoltage Protection
      9. 7.3.9  Out-of-Bounds Operation
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 Standby Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Output Voltage Set Point
          2. 8.2.2.1.2 Switching Frequency and Mode Selection
          3. 8.2.2.1.3 Inductor Selection
          4. 8.2.2.1.4 Output Capacitor Selection
          5. 8.2.2.1.5 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-7E6B6A0D-E4F8-4C7F-B3E8-510FC2B25D16-low.gif Figure 5-1 RNN Package18-Pin VQFN
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 BOOT I Supply input for the gate drive voltage of the high-side MOSFET. Connect a 0.1-µF bootstrap capacitor between BOOT and SW.
2,11 VIN P Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and PGND.
3, 4, 5,
8, 9, 10		 PGND G Power GND terminal for the controller circuit and the internal circuitry.
6, 7 SW O Switch node terminal. Connect the output inductor to this pin.
12 AGND G Ground of internal analog circuitry. Connect AGND to PGND plane.
13 FB I Converter feedback input. Connect to the resistor divider between output voltage and AGND.
14 SS O

Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external capacitor is connected, the soft-start time in 1ms.
15 EN I Enable input control, leaving this pin floating enables the converter. It can also be used to adjust the input UVLO by connecting to the resistor divider between VIN and EN.
16 PGOOD O Open Drain Power Good Indicator, it is asserted low if output voltage is out of PGOOD threshold, Overvoltage or if the device is under thermal shutdown, EN shutdown or during soft start.
17 VREG5 I/O 4.7-V internal LDO output which can also be driven externally with a 5V input. This pin supplies voltage to the internal circuitry and gate driver. Bypass this pin with a 4.7-μF capacitor.
18 MODE I Switching Frequency, Current Limit selection and Light load operation mode selection pin. Connect this pin to a resistor divider from VREG5 and AGND for different MODE options shown in table 4.