JAJSCL3C October   2016  – August 2023 TPS568215

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation and D-CAP3 Control Mode
      2. 7.3.2  Eco-mode Control
      3. 7.3.3  4.7 V LDO and External Bias
      4. 7.3.4  MODE Selection
      5. 7.3.5  Soft Start and Pre-biased Soft Start
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Power Good
      8. 7.3.8  Overcurrent Protection and Undervoltage Protection
      9. 7.3.9  Out-of-Bounds Operation
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 Standby Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Output Voltage Set Point
          2. 8.2.2.1.2 Switching Frequency and Mode Selection
          3. 8.2.2.1.3 Inductor Selection
          4. 8.2.2.1.4 Output Capacitor Selection
          5. 8.2.2.1.5 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 Layout Example

Figure 8-19 shows the recommended top side layout. Component reference designators are the same as the circuit shown in Figure 8-1. Resistor divider for EN is not used in the circuit of Figure 8-1, but are shown in the layout for reference.

GUID-F3259261-62FA-4517-90ED-2300E3736295-low.gifFigure 8-19 Top Side Layout

Figure 8-20 shows the recommended layout for the first internal layer. It is comprised of a large PGND plane and a smaller ANGD island. AGND and PGND are connected at a single point to reduce circulating currents.

GUID-66A0BE0E-C4CD-4488-B1BF-E908B505B35B-low.gifFigure 8-20 Mid Layer 1 Layout

Figure 8-21 shows the recommended layout for the second internal layer. It is comprised of a large PGND plane, a smaller copper fill area to connect the two top side VIN copper areas and a second VOUT copper fill area.

GUID-F3A90FA9-2FDE-45A5-96B5-F66B8ACF9CE8-low.gifFigure 8-21 Mid Layer 2 Layout

Figure 8-22 shows the recommended layout for the bottom layer. It is comprised of a large PGND plane and a trace to connect the BOOT capacitor to the SW node.

GUID-7E04DCEA-C8EF-4F16-9A06-4AD8707638D4-low.gifFigure 8-22 Bottom Layer Layout