JAJSOG6 October   2022 TPS568231

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation and D-CAP3™ Control Mode
      2. 7.3.2  Eco-mode™ Control
      3. 7.3.3  4.7-V LDO
      4. 7.3.4  MODE Selection
      5. 7.3.5  Soft Start and Prebiased Soft Start
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Power Good
      8. 7.3.8  Overcurrent Protection and Undervoltage Protection
      9. 7.3.9  UVLO Protection
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 Standby Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Output Voltage Set Point
          2. 8.2.2.1.2 Switching Frequency and MODE Selection
          3. 8.2.2.1.3 Inductor Selection
          4. 8.2.2.1.4 Output Capacitor Selection
          5. 8.2.2.1.5 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

  • Use a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3-inch, four-layer PCB with 2-oz copper is used as an example.
  • VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat dissipation.
  • Place equal capacitors on each side of the IC. Place them right from each VIN to PGND pin as close as possible to the device on the same side of the PCB.
  • Use vias near both VIN pins and provide a low impedance connection between them through an internal layer.
  • Use multiple vias near both PGND pins and use the layer directly below the device to connect them together, which helps to minimize noise and can help heat dissipation.
  • Inner layer 1 is ground with the PGND to AGND net tie.
  • Inner layer 2 has VIN copper pour that has vias to the top layer VIN.
  • Bottom layer is GND with the BOOT trace routing.
  • Reference feedback to the quiet AGND and route away from the switch node. Also keep feedback resistors and the feedforward capacitor near the IC.