JAJSOS6 November 2023 TPS568236
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT SUPPLY (VIN) | ||||||
VIN | Input voltage range | VIN | 4.5 | 18 | V | |
IVIN | VIN supply current (Quiescent) | No load, VEN = 3.3 V, non-switching | 84 | µA | ||
IINSDN | VIN shutdown current | No load, VEN = 0 V, PG open | 3.7 | µA | ||
UVLO | ||||||
VVCC UVLO_R | VCC undervoltage lockout | VVCC rising | 4.2 | 4.42 | V | |
VVCC UVLO_F | VCC undervoltage lockout | VVCC falling | 3.65 | 3.85 | V | |
VVCC UVLO_H | VCC undervoltage lockout | Hysteresis VCC voltage | 350 | 650 | mV | |
ENABLE (EN), MODE | ||||||
VEN_R | EN threshold high-level | VEN rising | 1.31 | 1.5 | V | |
VEN_F | EN threshold low-level | VEN falling | 1.0 | 1.13 | V | |
VEN_H | EN threshold low-level | Hysteresis | 180 | mV | ||
IEN | EN pulldown current | VEN = 0.8 V | 1.3 | 2.3 | uA | |
VIL;MODE | Low-level input voltage at MODE Pin | 0.4 | V | |||
VIH;MODE | High-level input voltage at MODE Pin | 0.8 | V | |||
IMODE | MODE pulldown current | VMODE = 0.8 V | 1.3 | 2.3 | 3.5 | uA |
VCC | ||||||
VVCC | VCC output voltage | VVIN > 5.2 V, IVCC ≤ 1 mA | 4.85 | 5 | 5.15 | V |
FEEDBACK VOLTAGE (FB) | ||||||
VFB_REG | Feedback regulation voltage | TJ = 25°C | 594 | 600 | 606 | mV |
Feedback regulation voltage | –40°C ≤ TJ ≤ 125°C | 591 | 600 | 609 | mV | |
DUTY CYCLE and FREQUENCY CONTROL | ||||||
fSW | Switching frequency | CCM operation | 600 | kHz | ||
tON(min) | Minimum ON pulse width | TJ = 25°C | 65 | 75 | ns | |
tOFF(min) | Minimum OFF pulse width | TJ = 25°C | 190 | ns | ||
SOFT-START | ||||||
tSS | Internal fixed soft start | 0.55 | 1 | 1.35 | ms | |
ISS | Soft Start charge current | 4 | 5 | 6 | μA | |
POWER SWITCHES (SW) | ||||||
RDSON(HS) | High-side MOSFET on-resistance | TJ = 25°C | 22 | mΩ | ||
RDSON(LS) | Low-side MOSFET on-resistance | TJ = 25°C | 11 | mΩ | ||
CURRENT LIMIT | ||||||
IOCL | Low-side valley current limit | Valley current limit on LS FET | 9.5 | 11 | 12.5 | A |
INOCL | Low-side negative current limit | Sinking current limit on LS FET | 3.9 | A | ||
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION | ||||||
VOVP | OVP trip threshold | 117 | 120 | 123 | % | |
tOVPDLY | OVP prop deglitch | 20 | μs | |||
tOVPDLY | OVP latch-off prop deglitch | 256 | μs | |||
VUVP | UVP trip threshold | 55 | 60 | 65 | % | |
tUVPDLY | UVP prop deglitch | 256 | μs | |||
POWER GOOD (PG) | ||||||
tPGDLY | PG start-up delay | PG from low to high | 500 | μs | ||
tPGDLY | PG delay time when VFB rising (fault) | PG from high to low | 20 | μs | ||
tPGDLY | PG delay time when VFB falling (fault) | PG from high to low | 28 | μs | ||
VPGTH | PG threshold when VFB falling (fault) | VFB falling (fault), percentage of VFB | 79 | 85 | 89 | % |
VPGTH | PG threshold when VFB rising (good) | VFB rising (good), percentage of VFB | 86 | 90 | 94 | % |
VPGTH | PG threshold when VFB rising (fault) | VFB rising (fault), percentage of VFB | 116 | 120 | 124 | % |
VPGTH | PG threshold when VFB falling (good) | VFB falling (good), percentage of VFB | 109 | 115 | 119 | % |
IPGMAX | PG sink current | VPG = 0.5 V | 50 | mA | ||
IPGLK | PG leak current | VPG = 5.5 V | 1 | μA | ||
OUTPUT DISCHARGE | ||||||
RDIS | Discharge resistance | TJ = 25 °C, VEN = 0 V | 160 | Ω | ||
THERMAL SHUTDOWN | ||||||
TJ(SD) | Thermal shutdown threshold | 165 | °C | |||
TJ(HYS) | Thermal shutdown hysteresis (1) | 20 | °C |