JAJSOS6 November   2023 TPS568236

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  PWM Operation and D-CAP3 Control Mode
      2. 6.3.2  VCC LDO
      3. 6.3.3  Soft Start
      4. 6.3.4  Enable Control
      5. 6.3.5  Power Good
      6. 6.3.6  Overcurrent Protection and Undervoltage Protection
      7. 6.3.7  UVLO Protection
      8. 6.3.8  Overvoltage Protection
      9. 6.3.9  Output Voltage Discharge
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 MODE Pin
      2. 6.4.2 Forced Continuous Conduction Operation
      3. 6.4.3 Power Save Mode (PSM)
  8. 7  Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Selection
          1. 7.2.2.1.1 Inductor Selection
          2. 7.2.2.1.2 Output Capacitor Selection
          3. 7.2.2.1.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4 Thermal Information

THERMAL METRIC(1) DEVICE UNIT
RJNR (QFN, JEDEC) RJNR (QFN, TI EVM)
12 PINS 12 PINS
RθJA Junction-to-ambient thermal resistance 72.7 37.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.1 Not Applicable (2) °C/W
RθJB Junction-to-board thermal resistance 18.7 Not Applicable (2) °C/W
ψJT Junction-to-top characterization parameter 1.8 3.7 °C/W
ψJB Junction-to-board characterization parameter 18.4 18.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The thermal simulation setup is not applicable to a TI EVM layout.