JAJSF14G March 2016 – August 2024 TPS56C215
PRODUCTION DATA
Figure 7-19 shows the recommended top side layout. Component reference designators are the same as the circuit shown in Figure 7-1. Resistor divider for EN is not used in the circuit of Figure 7-1, but are shown in the layout for reference.
Figure 7-20 shows the recommended layout for the first internal layer. It is comprised of a large PGND plane and a smaller ANGD island. AGND and PGND are connected at a single point to reduce circulating currents.
Figure 7-21 shows the recommended layout for the second internal layer. It is comprised of a large PGND plane, a smaller copper fill area to connect the two top side VIN copper areas and a second VOUT copper fill area.
Figure 7-22 shows the recommended layout for the bottom layer. It is comprised of a large PGND plane and a trace to connect the BOOT capacitor to the SW node.