The TPS6020x step-up, regulated charge pumps generate a 3.3-V ±4% output voltage from a 1.8-V to 3.6-V input voltage. The devices are typically powered by two Alkaline, NiCd or NiMH battery cells and operate down to a minimum supply voltage of
1.6 V. Continuous output current is a minimum of 100 mA for the TPS60200 and TPS60201 and 50 mA for the TPS60202 and TPS60203, all from a 2-V input. Only four external capacitors are needed to build a complete low-ripple DC/DC converter. The push-pull operating mode of two single-ended charge pumps assures the low output voltage ripple as current is continuously transferred to the output.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS6020x | MSOP (10) | 3.00 mm × 3.00 mm |
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Typical Application with Low-Battery Warning |
TPS60200 Peak Output Current |
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Changes from * Revision (March 2000) to A Revision
PART NUMBER | DEVICE FEATURES | OUTPUT CURRENT (mA) | OUTPUT VOLTAGE (V) | TA |
---|---|---|---|---|
TPS60200 | Low-battery detector | 100 | 3.3 | –40°C to 85°C |
TPS60201 | Power-good detector | 100 | 3.3 | –40°C to 85°C |
TPS60202 | Low-battery detector | 50 | 3.3 | –40°C to 85°C |
TPS60203 | Power-good detector | 50 | 3.3 | –40°C to 85°C |
PART NUMBER | DESCRIPTION |
---|---|
TPS60100 | 2-cell to regulated 3.3 V, 200-mA low-noise charge pump |
TPS60101 | 2-cell to regulated 3.3 V, 100-mA low-noise charge pump |
TPS60110 | 3-cell to regulated 5 V, 300-mA low-noise charge pump |
TPS60111 | 3-cell to regulated 5 V, 150-mA low-noise charge pump |
TPS60120 | 2-cell to regulated 3.3 V, 200-mA high-efficiency charge pump with low battery comparator |
TPS60121 | 2-cell to regulated 3.3 V, 200-mA high-efficiency charge pump with power-good comparator |
TPS60122 | 2-cell to regulated 3.3 V, 100-mA high-efficiency charge pump with low battery comparator |
TPS60123 | 2-cell to regulated 3.3 V, 100-mA high-efficiency charge pump with power-good comparator |
TPS60130 | 3-cell to regulated 5 V, 300-mA high-efficiency charge pump with low battery comparator |
TPS60131 | 3-cell to regulated 5 V, 300-mA high-efficiency charge pump with power-good comparator |
TPS60132 | 3-cell to regulated 5 V, 150-mA high-efficiency charge pump with low battery comparator |
TPS60133 | 3-cell to regulated 5 V, 150-mA high-efficiency charge pump with power-good comparator |
TPS60140 | 2-cell to regulated 5 V, 100-mA charge pump voltage tripler with low battery comparator |
TPS60141 | 2-cell to regulated 5 V, 100-mA charge pump voltage tripler with power-good comparator |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | TPS60200, TPS60202 |
TPS60201, TPS60203 |
||
C1+ | 4 | 4 | — | Positive terminal of the flying capacitor C1 |
C1– | 3 | 3 | — | Negative terminal of the flying capacitor C1 |
C2+ | 6 | 6 | — | Positive terminal of the flying capacitor C2 |
C2– | 8 | 8 | — | Negative terminal of the flying capacitor C2 |
EN | 9 | 9 | I | Device-enable input. Three operating modes can be programmed with the EN pin. EN = Low disables the device. Output and input are isolated in the shutdown mode and the output capacitor is automatically discharged. EN = High lets the device run from the internal oscillator. If an external clock signal is applied to the EN pin, the device is in Sync–Mode and runs synchronized at the frequency of the external clock signal. |
GND | 2 | 1, 2 | Ground | |
IN | 7 | 7 | I | Supply input. Bypass IN to GND with a capacitor of the same size as CO. |
LBI | 1 | — | I | Low-battery detector input for TPS60200 and TPS60202. A low-battery warning is generated at the LBO pin when the voltage on LBI drops below the threshold of 1.18 V. Connect LBI to GND if the low-battery detector function is not used. For the devices TPS60201 and TPS60203, this pin has to be connected to ground (GND pin). |
LBO | 10 | — | O | Open-drain low-battery detector output for TPS60200 and TPS60202. This pin is pulled low if the voltage on LBI drops below the threshold of 1.18 V. A pullup resistor should be connected between LBO and OUT or any other logic supply rail that is lower than 3.6 V. |
OUT | 5 | 5 | O | Regulated 3.3-V power output. Bypass OUT to GND with the output filter capacitor CO. |
PG | — | 10 | O | Open-drain power-good detector output for TPS60201 and TPS60203. As soon as the voltage on OUT reaches about 90% of it is nominal value this pin goes active high. A pullup resistor should be connected between PG and OUT or any other logic supply rail that is lower than 3.6 V. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN, OUT, EN, LBI, LBO, PG to GND | –0.3 | 3.6 | V |
C1+, C2+ to GND | –0.3 | VO + 0.3 | ||
C1–, C2– to GND | –0.3 | VI + 0.3 | ||
Continuous total power dissipation | TA ≤ 25°C power rating | 424 | mW | |
TA = 70°C power rating | 187 | |||
TA = 85°C power rating | 136 | |||
Continuous output current | TPS60200, TPS60201 | 150 | mA | |
TPS60202, TPS60203 | 75 | |||
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VI | Input voltage | 1.6 | 3.6 | V | |
Ci | Input capacitor | 2.2 | µF | ||
C1, C2 | Flying capacitors | 1 | µF | ||
CO | Output capacitor | 2.2 | µF | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS6020x | UNIT | |
---|---|---|---|
DGS (MSOP) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 158.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 49.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 78.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 4.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 76.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IO(MAX) | Maximum continuous output current | TPS60200 and TPS60201, VI = 2 V | 100 | mA | ||
TPS60202 and TPS60203, VI = 2 V | 50 | |||||
VO | Output voltage | 1.6 V < VI < 1.8 V, 0 < IO < 0.25 × IO(MAX) |
3 | V | ||
1.8 V < VI < 2 V, 0 < IO < 0.5 × IO(MAX) |
3.17 | 3.43 | ||||
2 V < VI < 3.3 V, 0 < IO < IO(MAX) | 3.17 | 3.43 | ||||
3.3 V < VI < 3.6 V, 0 < IO < IO(MAX) | 3.17 | 3.47 | ||||
VPP | Output voltage ripple | IO = IO(MAX) | 5 | mVPP | ||
I(Q) | Quiescent current (no-load input current) | IO = 0 mA, VI = 1.8 V to 3.6 V | 35 | 70 | µA | |
I(SD) | Shutdown supply current | EN = 0 V | 0.05 | 1 | µA | |
f(OSC) | Internal switching frequency | 200 | 300 | 400 | kHz | |
f(SYNC) | External clock signal frequency | 400 | 600 | 800 | kHz | |
External clock signal duty cycle | 30% | 70% | ||||
VIL | EN input low voltage | VI = 1.6 V to 3.6 V | 0.3 × VI | V | ||
VIH | EN input leakage current | VI = 1.6 V to 3.6 V | 0.7 × VI | V | ||
Ilkg(EN) | EN input leakage current | EN = 0 V or VI | 0.01 | 0.1 | µA | |
Output capacitor auto discharge time | EN is set from VI to GND, time until VO < 0.5 V |
0.6 | ms | |||
Output resistance in shutdown | EN = 0 V | 70 | Ω | |||
LinSkip threshold | VI = 2.2 V | 7 | mA | |||
Output load regulation | 10 mA < IO< IO(MAX), TA = 25°C | 0.01% | mA | |||
Output line regulation | 2 V < VI < 3.3 V, IO = 0.5 × IO(MAX), TA = 25°C |
0.6% | V | |||
I(SC) | Short-circuit current | VI = 2.4 V, VO = 0 V | 60 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
V(LBI) | LBI trip voltage | VI = 1.6 V to 2.2 V, TC = 0°C to 70°C |
1.13 | 1.18 | 1.23 | V |
LBI trip voltage hysteresis | For rising voltage at LBI | 10 | mV | |||
II(LBI) | LBI input current | V(LBI) = 1.3 V | 2 | 50 | nA | |
VO(LBO) | LBO output voltage low | V(LBI) = 0 V, I(LBO) = 1 mA | 0.4 | V | ||
Ilkg(LBO) | LBO leakage current | V(LBI) = 1.3 V, V(LBO) = 3.3 V | 0.01 | 0.1 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
V(PG) | Power-good trip voltage | TC = 0°C to 70°C | 0.87 × VO | 0.91 × VO | 0.95 × VO | V |
Vhys(PG) | Power-good trip voltage hysteresis | VO decreasing, TC = 0°C to 70°C | 1% | |||
VO(PG) | Power-good output voltage low | VO = 0 V, I(PG) = 1 mA | 0.4 | V | ||
Ilkg(PG) | Power-good leakage current | VO = 3.3 V, V(PG) = 3.3 V | 0.01 | 0.1 | µA |
The TPS6020x charge pumps provide a regulated 3.3-V output from a 1.8-V to 3.6-V input. They deliver up to 100-mA load current while maintaining the output at 3.3 V ± 4%. Designed specifically for space-critical, battery-powered applications, the complete converter requires only four external capacitors. The device is using the push-pull topology to achieve lowest output voltage ripple. The converter is also optimized for smallest board space. It makes use of small-sized capacitors, with the highest output current rating per output capacitance and package size.
The TPS6020x circuits consist of an oscillator, a 1.18-V voltage reference, an internal resistive feedback circuit, an error amplifier, two charge pump power stages with high current MOSFET switches, a shutdown and start-up circuit, a control circuit, and an auto-discharge transistor (see Functional Block Diagrams).
During start-up, that is when EN is set from logic low to logic high, the output capacitor is directly connected to IN and charged up with a limited current until the output voltage VO reaches 0.8 × VI. When the start-up comparator detects this limit, the converter begins switching. This precharging of the output capacitor guarantees a short start-up time. In addition, the inrush current into an empty output capacitor is limited. The converter can start into a full load, which is defined by a 33-Ω or 66-Ω resistor, respectively.
Driving EN low disables the converter. This disables all internal circuits and reduces the supply current to only 0.05 μA. The device exits shutdown once EN is set high. When the device is disabled, the load is isolated from the input. This is an important feature in battery-operated products because it extends the products shelf life.
Additionally, the output capacitor will automatically be discharged after EN is taken low. This ensures that the system, when switched off, is in a stable and reliable condition because the supply voltage is removed from the supply pins.
The operating frequency of the charge pump is limited to 400 kHz to avoid interference in the sensitive 455-kHz IF band. The device can either run from the integrated oscillator, or an external clock signal can be used to drive the charge pump. The maximum frequency of the external clock signal is 800 kHz. The switching frequency used internally to drive the charge pump power stages is half of the external clock frequency. The external clock signal is applied to the EN pin. The device will switch off if the signal on EN is hold low for more than 10 μs.
When the load current drops below the LinSkip current threshold, the devices will enter the pulse-skip mode but stay synchronized to the external clock signal.
The power-good output is an open-drain output that pulls low when the output is out of regulation. When the output rises to within 90% of its nominal voltage, the power-good output is released. Power-good is high impedance in shutdown. In normal operation, an external pullup resistor must be connected between PG and OUT, or any other voltage rail in the appropriate range. The resistor should be in the 100-kΩ to 1-MΩ range. If the PG output is not used, it should remain unconnected.
The two single-ended charge pump power stages operate in the so-called push-pull operating mode, that is they operate with a 180°C phase shift. Each single-ended charge pump transfers charge into its transfer capacitor (C1 or C2) in one half of the period. During the other half of the period (transfer phase), the transfer capacitor is placed in series with the input to transfer its charge to CO. While one single-ended charge pump is in the charge phase, the other one is in the transfer phase. This operation assures an almost constant output current which ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times the input voltage (hence the name voltage doubler). To provide a regulated fixed output voltage of 3.3 V, the TPS6020x devices use either pulse-skip or constant-frequency linear-regulation control mode. The mode is automatically selected based on the output current. If the load current is below the LinSkip current threshold, it switches into the power-saving pulse-skip mode to boost efficiency at low output power.
When the output current is higher then the LinSkip current threshold, the charge pump runs continuously at the switching frequency f(OSC). The control circuit, fed from the error amplifier, controls the charge on C1 and C2 by controlling the gates and hence the rDS(ON) of the integrated MOSFETs. When the output voltage decreases, the gate drive increases, resulting in a larger voltage across C1 and C2. This regulation scheme minimizes output ripple. Since the device switches continuously, the output signal contains well-defined frequency components, and the circuit requires smaller external capacitors for a given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light loads. For this reason, the device switches seamlessly into the pulse-skip mode when the output current drops below the LinSkip current threshold.
The regulator enters the pulse-skip mode when the output current is lower than the LinSkip current threshold of
7 mA. In the pulse-skip mode, the error amplifier disables switching of the power stages when it detects an output voltage higher than 3.3 V. The controller skips switching cycles until the output voltage drops below 3.3 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again. A 30-mV output voltage offset is introduced in this mode.
The pulse-skip regulation mode minimizes operating current because it does not switch continuously and deactivates all functions except the voltage reference and error amplifier when the output is higher than 3.3 V. Even in pulse-skip mode the rDS(ON) of the MOSFETs is controlled. This way the energy per switching cycle that is transferred by the charge pump from the input to the output is limited to the minimum that is necessary to sustain a regulated output voltage, with the benefit that the output ripple is kept to a minimum. When switching is disabled from the error amplifier, the load is also isolated from the input.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The power-good output is an open-drain output that pulls low when the output is out of regulation. When the output rises to within 90% of its nominal voltage, the power-good output is released. Power-good is high impedance in shutdown. In normal operation, an external pullup resistor must be connected between PG and OUT, or any other voltage rail in the appropriate range. The resistor should be in the 100-k Ω to 1-M Ω range. If the PG output is not used, it should remain unconnected)
The TPS6020x devices require only four external capacitors to achieve a very low output voltage ripple. The capacitor values are closely linked to the required output current. Low ESR (<0.1 Ω) capacitors should be used at input and output. In general, the transfer capacitors (C1 and C2) will be the smallest, a 1-µF value is recommended for maximum load operation. With smaller capacitor values, the maximum possible load current is reduced and the LinSkip threshold is lowered.
The input capacitor improves system efficiency by reducing the input impedance. It also stabilizes the input current of the power source. The input capacitor should be chosen according to the power supply used and the distance from the power source to the converter IC. TI recommends Ci be about two to four times as large as the flying capacitors C1 and C2.
The output capacitor (Co) should be at minimum the size of the input capacitor. The minimum required capacitance is 2.2 μF. Larger values will improve the load transient performance and will reduce the maximum output ripple voltage.
Only ceramic capacitors are recommended for input, output, and flying capacitors. Depending on the material used to manufacture them, ceramic capacitors might lose their capacitance over temperature and voltage. Ceramic capacitors of type X7R or X5R material will keep their capacitance over temperature and voltage, whereas Z5U- or Y5V-type capacitors will decrease in capacitance. Table 3 lists the recommended capacitor values.
LOAD CURRENT, IL (mA) | FLYING CAPACITORS, C1/C2 (µF) | INPU CAPACITOR, Ci (µF) | OUTPUT CAPACITOR, Co (µF) | OUTPUT VOLTAGE RIPPLE IN LINEAR MODE, V(P-P) (mV) | OUTPUT VOLTAGE RIPPLE IN SKIP MODE, V(P-P) (mV) |
---|---|---|---|---|---|
0 to 100 | 1 | 2.2 | 2.2 | 3 | 20 |
0 to 100 | 1 | 4.7 | 4.7 | 3 | 10 |
0 to 100 | 1 | 2.2 | 10 | 3 | 7 |
0 to 100 | 2.2 | 4.7 | 4.7 | 3 | 10 |
0 to 50 | 0.47 | 2.2 | 2.2 | 3 | 20 |
0 to 25 | 0.22 | 2.2 | 2.2 | 5 | 15 |
0 to 10 | 0.1 | 2.2 | 2.2 | 5 | 15 |
Table 4 lists the capacitor selections to operate the device in the recommended operating conditions.
MANUFACTURER | PART NUMBER | SIZE | CAPACITANCE | TYPE |
---|---|---|---|---|
Taiyo Yuden | UMK212BJ104MG | 0805 | 0.1 µF | Ceramic |
Taiyo Yuden | EMK212BJ224MG | 0805 | 0.22 µF | Ceramic |
Taiyo Yuden | EMK212BJ474MG | 0805 | 0.47 µF | Ceramic |
Taiyo Yuden | LMK212BJ105KG | 0805 | 1 µF | Ceramic |
Taiyo Yuden | LMK212BJ225MG | 0805 | 2.2 µF | Ceramic |
Taiyo Yuden | EMK316BJ225KL | 1206 | 2.2 µF | Ceramic |
Taiyo Yuden | LMK316BJ475KL | 1206 | 4.7 µF | Ceramic |
Taiyo Yuden | JMK316BJ106ML | 1206 | 10 µF | Ceramic |
AVX | 0805ZC105KAT2A | 0805 | 1 µF | Ceramic |
AVX | 1206ZC225KAT2A | 1206 | 2.2 µF | Ceramic |
The low-battery comparator trips at 1.18 V ±4% when the voltage on pin LBI ramps down. The voltage V (TRIP) at which the low-battery warning is issued can be adjusted with a resistive divider as shown in Figure 4. The sum of resistors R1 and R2 is recommended to be in the 100-kΩ to 1-MΩ range. When choosing R1 and R2, be aware of the input leakage current into the LBI pin.
LBO is an open-drain output. TI recommends an external pullup resistor to OUT, or any other voltage rail in the appropriate range, in the 100-kΩ to 1-MΩ range. During start-up, the LBO output signal is invalid for the first 500 μs. LBO is high impedance when the device is disabled. If the low-battery comparator function is not used, connect LBI to ground and leave LBO unconnected. The low-battery detector is disabled when the device is switched off.
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A 100-nF ceramic capacitor should be connected in parallel to R2 if large line transients are expected. These voltage drops can inadvertently trigger the low-battery comparator and produce a wrong low-battery warning signal at the LBO pin.
Formulas to calculate the resistive divider for low-battery detection, with V LBI = 1.13 V to 1.23 V and the sum of resistors R1 and R2 equal 1 MΩ.
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Formulas to calculate the minimum and maximum battery voltage.
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V(IN)/V | R1/kΩ | R2/kΩ | VTRIP(MIN)/V | VTRIP(MAX)/V |
---|---|---|---|---|
1.6 | 267 | 750 | 1.524 | 1.677 |
1.7 | 301 | 681 | 1.62 | 1.785 |
1.8 | 340 | 649 | 1.71 | 1.887 |
1.9 | 374 | 619 | 1.799 | 1.988 |
2 | 402 | 576 | 1.903 | 2.106 |
The TPS6020x are designed to operate from a 1.6-V to 3.6-V input voltage supply. The input power supply's output current needs to be rated according to the output voltage and the output current of the power rail application.
Careful board layout is necessary due to the high transient currents and switching frequency of the converter. All capacitors should be placed in close proximity to the device. A PCB layout proposal for a one-layer board is given in Figure 21.
An evaluation module for the TPS60200 is available and can be ordered under product code TPS60200EVM–145. The EVM uses the layout shown in Figure 21. All components including the pins are shown. The EVM is built so that it can be connected to a 14-pin dual inline socket; therefore, the space needed for the IC, the external parts, and 8 pins is 17.9 mm × 10.2 mm = 182.6 mm2.
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IC1 | TPS60200 |
---|---|
C1, C2 | Flying capacitors |
C3 | Input capacitors |
C4 | Output capacitors |
C5(1) | Stabilization capacitor for LBI |
R1, R2 | Resistive divider for LBI |
R3 | Pullup resistor for LBO |
R4 | Pullup resistor for EN |
The power dissipated in the TPS6020x devices depends mainly on input voltage and output current and is approximated with Equation 5.
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By observing Equation 5, it can be seen that the power dissipation is worst for highest input voltage VI and highest output current IO. For an input voltage of 3.6 V and an output current of 100 mA the calculated power dissipation P(DISS) is 390 mW. This is also the point where the charge pump operates with its lowest efficiency.
With the recommended maximum junction temperature of 125°C and an assumed maximum ambient operating temperature of 85°C, the maximum allowed thermal resistance junction to ambient of the system is calculated with Equation 6.
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PDISS must be less than that allowed by the package rating. The thermal resistance junction to ambient of the used 10-pin MSOP is 294°C/W for an unsoldered package. The thermal resistance junction to ambient with the IC soldered to a printed circuit using a board layout as described in Application Information, the RθJA is typically 200°C/W, which is higher than the maximum value calculated above. However in a battery-powered application, both VI and TA will typically be lower than the worst-case ratings used in Equation 6, and power dissipation should not be a problem in most applications.
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