EasyScale is a simple, but flexible, one-pin interface to configure the current of the dual channels. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor and the device is the slave. Figure 6-5 and Table 6-1 give an overview of the protocol used by TPS61162A/TPS61163A. A command consists of 24 bits, including an 8-bit device address byte and a 16-bit data byte. All of the 24 bits should be transmitted together each time, and the LSB bit should be transmitted first. The device address byte D7(MSB)~D0(LSB) is fixed to 0x8F. The data byte includes 9 bits D8(MSB)~D0(LSB) for brightness information and an RFA bit. The RFA bit set to "1" indicates the Request for Acknowledge condition. The Acknowledge condition is only applied when the protocol is received correctly. The advantage of EasyScale compared with other one pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec.

Figure 6-5 Easyscale Protocol Overview

Figure 6-6 Easyscale Timing, With RFA = 0

Figure 6-7 Easyscale Timing, With RFA = 1

Figure 6-8 Easyscale — Bit Coding

The 24-bit command should be transmitted with LSB first and MSB last. Figure 6-6 shows the protocol without acknowledge request (Bit RFA = 0), Figure 6-7 with acknowledge request (Bit RFA = 1). Before the command transmission, a start condition must be applied. For this, the EN pin must be pulled high for at least t_start (2μs) before the bit transmission starts with the falling edge. If the EN pin is already at high level, no start condition is needed. The transmission of each command is closed with an End of Stream condition for at least t_EOS (2μs).

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t_LOW and t_HIGH (refer to Figure 6-8). It can be simplified to:

Low Bit (Logic 0): t_LOW ≥ 2 x t_HIGH

High Bit (Logic 1): t_HIGH ≥ 2 x t_LOW

The bit detection starts with a falling edge on the EN pin and ends with the next falling edge. Depending on the relation between t_HIGH and t_LOW, the logic 0 or 1 is detected.

The acknowledge condition is only applied if:

• Acknowledge is requested by setting RFA bit to 1.
• The transmitted device address matches with the device address of the IC.
• Total 24 bits are received correctly.

If above conditions are met, after t_valACK delay from the moment when the last falling edge of the protocol is detected, an internal ACKN-MOSFET is turned on to pull the EN pin low for the time t_ACKN, which is 512μs maximum, then the Acknowledge condition is valid. During the t_valACK delay, the master controller keeps the line low; after the delay, it should release the line by outputting high impedance and then detect the acknowledge condition. If it reads back a logic 0, it means the device has received the command correctly. The EN pin can be used again by the master when the acknowledge condition ends after t_ACKN time.

The acknowledge condition can only be requested when the master device has an open drain output. For a push-pull output stage, the use of a series resistor in the EN line to limit the current to 500μA is recommended to for such cases as:

• An accidentally requested acknowledge, or
• To protect the internal ACKN-MOSFET.