JAJS467F December   2008  – April 2019 TPS61175

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switching Frequency
      2. 7.3.2 Soft Start
      3. 7.3.3 Overcurrent Protection
      4. 7.3.4 Enable and Thermal Shutdown
      5. 7.3.5 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum ON Time and Pulse Skipping
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Determining the Duty Cycle
        3. 8.2.2.3  Selecting the Inductor
        4. 8.2.2.4  Computing the Maximum Output Current
        5. 8.2.2.5  Setting Output Voltage
        6. 8.2.2.6  Setting the Switching Frequency
        7. 8.2.2.7  Setting the Soft-Start Time
        8. 8.2.2.8  Selecting the Schottky Diode
        9. 8.2.2.9  Selecting the Input and Output Capacitors
        10. 8.2.2.10 Compensating the Small Signal Control Loop
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 開発サポート
      1. 11.2.1 WEBENCHツールによるカスタム設計の作成
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.4 Computing the Maximum Output Current

The over-current limit for the integrated power FET limits the maximum input current and thus the maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change the maximum current output (IOUT(MAX)). The current limit clamps the peak inductor current, therefore the ripple has to be subtracted to derive maximum DC current.

Equation 8. TPS61175 EQU.gif

where

  • ILIM = overcurrent limit
  • ηest= efficiency estimate based on similar applications or computed above

For instance, when VIN = 12 V is boosted to VOUT = 24 V, the inductor is 10 µH, the Schottky forward voltage is 0.4 V, and the switching frequency is 1.2 MHz; then the maximum output current is 1.2 A in typical condition, assuming 90% efficiency and a %RPL = 20%.