SLVSAQ2C January   2014  – October 2014 TPS61230 , TPS61232

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Startup
      2. 8.3.2 Current Limit Operation
      3. 8.3.3 Enable/Disable
      4. 8.3.4 Undervoltage Lockout
      5. 8.3.5 Output Capacitor Discharge, TPS61231
      6. 8.3.6 Power Good Output
      7. 8.3.7 Over Voltage Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boost Normal Mode
      2. 8.4.2 Boost Power Save Mode
      3. 8.4.3 Zero Duty Cycle Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS61230 2.3-V to 5.5-V Input, 5-V Output Converter
        1. 9.2.1.1 TPS61230 5-V Output Design Requirements
        2. 9.2.1.2 TPS61230 5-V Detailed Design Procedure
          1. 9.2.1.2.1 Programming the Output Voltage
          2. 9.2.1.2.2 Inductor and Capacitor Selection
            1. 9.2.1.2.2.1 Inductor Selection
            2. 9.2.1.2.2.2 Output Capacitor Selection
            3. 9.2.1.2.2.3 Input Capacitor Selection
          3. 9.2.1.2.3 Loop Stability, Feed Forward Capacitor
        3. 9.2.1.3 TPS61230 5-V Output Application Performance Plots
      2. 9.2.2 TPS61230 2.3-V to 5.5-V Input, 3.5-V Output Converter
        1. 9.2.2.1 TPS61230 3.5-V Output Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 TPS61230 3.5-V Output Application Performance Plots
      3. 9.2.3 TPS61230 Application with Feed Forward Capacitor for Best Transient Response
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage range at pins(2) EN, FB, PG, SS, HYS, VIN, VOUT, SW –0.3 7 V
Operating junction temperature range, TJ –40 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground pin.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range -65 150 °C
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2 2 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VIN Supply voltage at VIN pin 2.3 5.5 V
ISINK_PG Sink current at PG pin 500 µA
VPG Pull-up resistor voltage 5.5 V
TJ Operating junction temperature -40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS6123x UNIT
DRC (11 PINS)
RθJA Junction-to-ambient thermal resistance 49.1 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 57.2
RθJB Junction-to-board thermal resistance 26.6
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 23.8
RθJC(bottom) Junction-to-case(bottom) thermal resistance 4.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TJ = –40°C to 125°C and VIN = 3.6 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VUVLO Input under voltage lockout VIN falling 2.0 2.1 V
VIN rising 2.1 2.2
IQ Quiescent current into VIN IC enabled, No load, No switching
VOUT = 5 V, TJ = –40 °C to 85°C		 35 60 µA
IC enabled, No load
VIN = 4.2 V, VOUT = No supply, TJ = –40 °C to 85°C		 200 230
ISD Shutdown current into VIN 0 V ≤ VEN ≤ 0.4 V, VIN = 2.3 V to 5.5 V, TJ = -40 °C to 85°C 1.5 6 µA
Leakage current from SW to VOUT VEN = 0 V, VOUT = 0 V; VSW = VIN = 3.6 V 2.5 µA
OUTPUT
VOUT Output voltage range 2.5 5.5 V
VOUT Output voltage accuracy, TPS61232 PWM mode 4.9 5.0 5.1 V
VOUT Output voltage accuracy, TPS61232 PFM mode(1) 5.035 V
VFB Feedback voltage, TPS61230 and TPS61231 PWM mode 0.985 1 1.015 V
PFM mode(1) 1.007
FB pin leakage current VFB = 1 V 100 nA
RDIS Output discharge resistor
TPS61231		 VOUT = 5 V 200 Ω
VOVP Over voltage protection DC threshold VOUT rising 5.7 6 6.2 V
Over voltage protection hysteresis VOUT falling below VOVP 0.15
ISS Bias current in soft start phase After pre-charge phase 5 µA
Line regulation IOUT = 1 A, VIN = 2.3 V to 4.5 V 0.06 %/V
Load regulation IOUT = 0.5 A to 2 A 0.15 %/A
LOGIC INTERFACE
VTH_EN_ON EN pin threshold rising VIN = 2.3 V to 5.5 V 1.15 1.19 1.23 V
VTH_EN_OFF EN pin threshold falling VIN = 2.3 V to 5.5 V 1.11 1.14 1.18 V
VOL_HYS HYS pin low level voltage ISINK_HYS = 1 mA, VEN = 1.1 V 0.7 V
VTH_PG Power good DC threshold VOUT rising, referenced to VOUT_NOMINAL 93% 95% 99%
VOUT falling referenced to VOUT_NOMINAL 87% 90% 93%
VOL_PG PG pin low level voltage ISINK_PG = 500 µA 0.4 V
POWER STAGE
ILIM_SW Switch valley current limit 4.0 5.0 6.0 A
ILIM_Pre Precharge current limit VOUT = 5 V 2.0 2.8 3.5 A
VOUT = 3.5 V 1.8 2.6 3.3
VOUT = 0 V 0.4 0.55 0.7
RDS(on) High side MOSFET on resistance VOUT = 5 V 50 75 mΩ
Low side MOSFET on resistance VOUT = 5 V 50 75
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling below TJSD 20
(1) L = 1 µH, COUT = 20 µF (effective capacitance value)

7.6 Typical Characteristics

VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
C001_HSRdson_lvsaq2.png
Figure 1. High-Side MOSFET On Resistance vs Junction Temperature
C003_Vref_lvsaq2.png
Figure 3. Voltage Reference vs Junction Temperature
C014_EN_logic_lvsaq2.png
Figure 5. EN Logic Threshold vs Junction Temperature
C011_Isd_boost_lvsaq2.png
Figure 7. Shutdown Current vs Input Voltage (Boost Mode)
C015_SS_Curr_slvsaq2.png
Figure 9. Soft Start Charge Current vs Junction Temperature
C002_LSRDSON_lvsaq2.png
Figure 2. Low-Side MOSFET On Resistance vs Junction Temperature
C013_VIN_UVLO_lvsaq2.png
Figure 4. Vin UVLO Threshold vs Junction Temperature
C010_Iq_boost_lvsaq2.png
Figure 6. Quiescent Current vs Input Voltage (Boost Mode)
C012_Curr_lim_lvsaq2.png
Figure 8. Switch Valley Current Limit vs Input Voltage (Boost Mode)