JAJSCE8B July   2016  – October 2018 TPS61230A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      効率
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Startup
      2. 8.3.2 Enable and Disable
      3. 8.3.3 Under-Voltage Lockout (UVLO)
      4. 8.3.4 Current Limit Operation
      5. 8.3.5 Over Voltage Protection
      6. 8.3.6 Load Disconnect
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Mode
      2. 8.4.2 PFM Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS61230A 2.5-V to 4.5-V Input, 5-V Output Converter
        1. 9.2.1.1 TPS61230A 5-V Output Design Requirements
        2. 9.2.1.2 TPS61230A 5-V Detailed Design Procedure
          1. 9.2.1.2.1 Programming The Output Voltage
          2. 9.2.1.2.2 Inductor and Capacitor Selection
            1. 9.2.1.2.2.1 Inductor Selection
            2. 9.2.1.2.2.2 Output Capacitor Selection
            3. 9.2.1.2.2.3 Input Capacitor Selection
          3. 9.2.1.2.3 Loop Stability, Feed Forward Capacitor
        3. 9.2.1.3 TPS61230A 5-V Output Application Performance Plots
      2. 9.2.2 Systems Example - TPS61230A with Feed Forward Capacitor for Best Transient Response
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Typical Characteristics

VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
TPS61230A D009_SLVSCZ5.gif
TA = 25 ºC
Figure 1. Efficiency vs. Output Current
TPS61230A D015_SLVSCZ5.gif
TA = 25 ºC
Figure 3. Line Regulation
TPS61230A D013_SLVSCZ5.gif
TA = 25 ºC
Figure 5. Frequency vs. Load
TPS61230A D002_SLVSCZ5.gif
VOUT = 5 V VIN = 3.6V
Figure 7. Low-Side FET Rdson vs Junction Temperature
TPS61230A D017_SLVSCZ5.gif
Figure 9. Quiescent Current vs Input Voltage
TPS61230A D007_SLVSCZ5.gif
Figure 11. Vin UVLO Threshold vs Junction Temperature
TPS61230A D010_SLVSCZ5.gif
TA = 25 ºC
Figure 2. Efficiency vs. Input Voltage
TPS61230A D012_SLVSCZ5.gif
TA = 25 ºC
Figure 4. Load Regulation
TPS61230A D001_SLVSCZ5.gif
VOUT = 5 V VIN = 3.6V
Figure 6. High-Side FET Rdson vs Junction Temperature
TPS61230A D003_SLVSCZ5.gif
Figure 8. Voltage Reference vs Junction Temperature
TPS61230A D016_SLVSCZ5.gif
Figure 10. Switch Valley Current Limit vs Input Voltage
TPS61230A D008_SLVSCZ5.gif
Figure 12. EN logic Threshold vs Junction Temperature