JAJSVH7A October   2024  – November 2024 TPS61287

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Start-up
      2. 6.3.2 Undervoltage Lockout (UVLO)
      3. 6.3.3 Programmable EN/UVLO
      4. 6.3.4 Switching Valley Current Limit
      5. 6.3.5 External Clock Synchronization
      6. 6.3.6 Stackable Multi-phase Operation
      7. 6.3.7 Device Functional Modes
        1. 6.3.7.1 Forced PWM Mode
        2. 6.3.7.2 Auto PFM Mode
      8. 6.3.8 Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap And VCC Capacitors Selection
        4. 7.2.2.4 MOSFET Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.6 Output Capacitor Selection

Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR, high ripple current capacity, and small output voltage ripple.

When input voltage reaches the minimum value , there is the largest output voltage ripple caused by the capacitance. From the required output voltage ripple, use the following equations to calculate the minimum required effective capacitance COUT:

Equation 9. TPS61287
Equation 10. TPS61287

where

  • Vripple_dis is output voltage ripple caused by charging and discharging of the output capacitor.
  • Vripple_ESR is output voltage ripple caused by ESR of the output capacitor.
  • VIN_MIN is the minimum input voltage of boost converter.
  • VOUT is the output voltage.
  • IOUT is the output current.
  • ILpeak is the peak current of the inductor.
  • ƒSW is the converter switching frequency.
  • RC_ESR is the ESR of the output capacitors.
Note:

DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a strong influence on the final effective capacitance. Therefore, the right capacitor value must be chosen carefully. The differences between the rated capacitor value and the effective capacitance result from package size and voltage rating in combination with material. A 10-V rated 0805 capacitor with 10 μF can have an effective capacitance of less than 5 μF at an output voltage of 5 V.