JAJSO66A December   2023  – January 2024 TPS61289

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Bidirectional Operation Configuration
      2. 6.3.2 VCC Power Supply
      3. 6.3.3 VHIGH and VCC Undervoltage Lockout (UVLO)
      4. 6.3.4 Enable and Programmable EN/UVLO
      5. 6.3.5 Switching Frequency
      6. 6.3.6 Programmable Switching Peak and Valley Current Limit
      7. 6.3.7 External Clock Synchronization
      8. 6.3.8 VHIGH Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Bootstrap Capacitor Selection
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 MOSFET Selection
        4. 7.2.2.4 VLOW/VHIGH Output Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.7 External Clock Synchronization

The TPS61289 can synchronize to an external clock signal applied to the M/SYNC pin for noise-sensitive or multiphase applications. When an external clock signal is applied to the M/SYNC pin, the device switching frequency is forced to the external clock. The external clock frequency must be within ±20% of 250kHz. The external clock on the M/SYNC pin must have a low-level voltage less than 0.4V and a high-level voltage greater than 1.2V. A valid synchronous clock signal must be greater than 50ns wide and have a minimum of 4 consecutive clocks prior to synchronization.