JAJSO66A December 2023 – January 2024 TPS61289
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VLOW | VLOW voltage range | 23 | V | |||
VVHIGH | VHIGH voltage range | 4.5 | 25 | V | ||
VHIGH_UVLO | Under voltage lockout threshold | VHIGH_UVLO rising | 3.2 | 3.4 | 3.6 | V |
VHIGH_UVLO | Under voltage lockout threshold | VHIGH_UVLO falling | 2.9 | 3.1 | 3.3 | V |
VCC | Internal regulator output | IVCC = 15mA | 5.1 | V | ||
VCC_UVLO | VCC UVLO threshold | VCC rising | 2.3 | V | ||
VCC_UVLO | VCC UVLO threshold | VCC falling | 2.15 | V | ||
VCC_HYS | VCC UVLO hysteresis | VCC hysteresis | 0.15 | V | ||
ISD_VLOW |
Shutdown current into VLOW pin | IC disabled, VLOW = SW = 2.3V to 23V, TJ up to 85°C | 1.5 | 6 | µA | |
ISD_SW | Shutdown current into SW pin | IC disabled, VLOW = SW = 2.3V to 23V, TJ up to 85°C | 0.2 | 4 | µA | |
IFB_LKG | Leakage current into FB pin | 50 | nA | |||
LOGIC INTERFACE | ||||||
VEN_H | EN high-level voltage threshold | VCC = 5.0V | 1.15 | V | ||
VEN_L | EN low-level voltage threshold | VCC = 5.0V | 0.4 | V | ||
VEN/UVLO_RISE | UVLO rising threshold at the EN/UVLO | VCC = 5.0V | 1.20 | 1.23 | 1.27 | V |
IEN/UVLO | Sourcing current at the EN/UVLO pin | VEN/UVLO = 1.3V | 4.4 | 5 | 5.6 | µA |
VMODE_H | MODE high-level voltage threshold | VCC = 5.0V | 1.2 | V | ||
VMODE_L | MODE low-level voltage threshold | VCC = 5.0V | 0.4 | V | ||
OUTPUT | ||||||
VREF | Reference voltage at the FB pin | PWM mode | 0.985 | 1 | 1.015 | V |
VHIGH_OVP | VHIGH overvoltage protection threshold | VHIGH OVP rising | 26 | 27 | 28 | V |
VHIGH_OVP_HYS | VHIGH OVP protection hysteresis | 1 | V | |||
POWER SWITCH | ||||||
RDS(on) | High-side MOSFET on resistance | VCC = 5.0V | 8.5 | mΩ | ||
FSW |
FSW when VLOW > 1.7V | VLOW = 3.6V | 250 | kHz | ||
FSW when 0.5V < VLOW < 1.5V | VLOW = 1.2V | 100 | kHz | |||
FSW when VLOW < 0.5V | VLOW = 0.3V | 50 | kHz | |||
tOFF_min | Minimum off time in boost mode | 90 | 130 | ns | ||
tON_min | Minimum on time in buck mode | 90 | 130 | ns | ||
tDLH | LS-GATE off to HS-GATE on deadtime | 35 | ns | |||
tDHL | HS-GATE off to LS-GATE on deadtime | 25 | ns | |||
ILIM |
High clamp valley current limit(boost mode) | RILIM = 20kΩ | 17 | 20 | 23 | A |
Low clamp valley current limit(boost mode) | -3.3 | A | ||||
High clamp peak current limit(buck mode) | RILIM = 20kΩ | 17 | 20 | 23 | A | |
Low clamp peak current limit(buck mode) | -1.5 | A | ||||
SOFT START | ||||||
tSS | Soft start time of internal reference | 8 | ms | |||
ERROR AMPLIFIER | ||||||
ISINK | COMP pin sink current | VFB = VREF + 400mV, VCOMP = 1.5V | 20 | µA | ||
ISOURCE | COMP pin source current | VFB = VREF - 400mV, VCOMP = 1.5V | 20 | µA | ||
VCOMPH | High clamp voltage at the COMP pin | RILIM = 20kΩ , PWM mode | 1.6 | V | ||
VCOMPL | Low clamp voltage at the COMP pin | 0.6 | V | |||
GEA | Error amplifier transconductance | VCC = 5.0V | 180 | µA/V | ||
SYNCHRONOUS CLOCK | ||||||
RSYNC | Internal pull down resistor from SYNC pin | 800 | kΩ | |||
VM/SYNC_H | M/SYNC high-level voltage threshold | 1.2 | V | |||
VM/SYNC_L | M/SYNC low-level voltage threshold | 0.4 | V | |||
TSYNC_MIN | Minimum sync clock pulse width | 50 | ns | |||
PROTECTION | ||||||
TSD | Thermal shutdown | Junction temperature rising | 160 | °C | ||
TSD_HYS | Thermal shutdown hysteresis | 20 | °C |