JAJSFB0E January   2018  – February 2024 TPS61322

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Boost Controller Circuit
      3. 7.3.3 21
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Current Limit Operation
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Boost without Schottky Diode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Maximum Output Current
          3. 8.2.1.2.3 Inductor Selection
          4. 8.2.1.2.4 35
          5. 8.2.1.2.5 Capacitor Selection
          6. 8.2.1.2.6 37
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Boost with Schottky Diode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Inductor Selection
          2. 8.2.2.2.2 Schottky Diode Selection
          3. 8.2.2.2.3 Capacitor Selection
        3. 8.2.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Detail Design Schematics
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.2.1.2.5 Capacitor Selection

For better output voltage filtering, TI recommends low ESR X5R or X7R ceramic capacitors.

For the output capacitor at the VOUT pin, TI recommends small ceramic capacitors. Place the capacitors as close as possible to the VOUT and GND pins of the device to depress the SW spike. The device can normally work with SW negative spike of -0.7V within 1ns. However, larger negative spike may potentially shoot the MOSFET inside. If, for any reason, the application requires the use of large capacitors that cannot be placed close to the device, the use of a small ceramic capacitor with a capacitance value of 1μF in parallel to the large one is recommended. Place this small capacitor as close as possible to the VOUT and GND pins of the device.

Considering loop stability, for inductance of 4.7 µH, the minimal output capacitor value is 10 μF (effective value). Refer to Table 8-3 for inductor and capacitor combination. Increasing the output capacitor makes the output ripple smaller.

When selecting capacitors, ceramic capacitor’s derating effect under DC bias voltage must be considered. Choose the right nominal capacitance by checking capacitor's DC bias characteristics. In this example, GRM188R60J106ME84D, which is a 10-µF ceramic capacitor with high effective capacitance value at DC biased condition, is selected for VOUT rail. Two 10-μF capacitors in parallel are recommended to get the desired effective capacitance.