The TPS61372 uses the peak current with adaptive off-time control topology. With the inductor current information sensed, the small-signal model of the power stage reduces from a two-pole system, created by L and C_OUT, to a single-pole system, created by R_OUT and C_OUT. An external loop compensation network connecting to the COMP pin of TPS61372 is added to optimize the loop stability and the response time, a resistor R_C, capacitor C_C, and C_P shown in Figure 8-2 comprises the loop compensation network.

Figure 8-2 TPS61372 Control Equivalent Circuitry Model

The small signal of power stage including the slope compensation is:

Equation 11.

where

• D is the duty cycle
• R_OUT is the output load resistor
• R_SENSE is the equivalent internal current sense resistor, which is typically 0.2 Ω of TPS61372

The single pole of the power stage is:

Equation 12.

where

• C_OUT is the output capacitance, for a boost converter having multiple, identical output capacitors in parallel, simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor is:

Equation 13.

where

• R_ESR is the equivalent resistance in series of the output capacitor

The right-hand plane zero is:

Equation 14.

where

• D is the duty cycle
• R_OUT is the output load resistor
• L is the inductance

The TPS61372 COMP pin is the output of the internal trans-conductance amplifier.

Equation 15 shows the equation for feedback resistor network and the error amplifier.

Equation 15.

where

• R_EA is the output impedance of the error amplifier R_EA = 500 MΩ. G_EA is the transconuctance of the error amplifier, G_EA = 175 μS.
• ƒ_P1, ƒ_P2 is the pole's frequency of the compensation
• f_Z is the zero’s frequency of the compensation network

Equation 16.

where

• C_C is the zero capacitor compensation

Equation 17.

where

• C_P is the pole capacitor compensation
• R_C is the resistor of the compensation network

Equation 18.