JAJSSX0B January   2022  – January 2024 TPS61376

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VCC Power Supply
      2. 6.3.2 Enable and Programmable UVLO
      3. 6.3.3 Soft Start and Inrush Current Control During Start-Up
      4. 6.3.4 Switching Frequency
      5. 6.3.5 Adjustable input average Current Limit
      6. 6.3.6 Shut Down and Load Disconnect
      7. 6.3.7 Overvoltage Protection
      8. 6.3.8 Output Short Protection
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Auto PFM Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap Capacitor Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Output Capacitor Selection
        6. 7.2.2.6 Diode Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.7 Loop Stability

The TPS61376 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.

The power stage small signal loop response of constant off-time (COT) with peak current control can be modeled by Equation 12.

Equation 12. GUID-55FFB7F9-AD03-4DFF-894D-D01603D3332A-low.gif

where

  • D is the switching duty cycle.
  • RO is the output load resistance.
  • KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 6.5A/V.
Equation 13. GUID-1B5CE2AC-22F3-454D-A27B-E66AA4B25E32-low.gif

where

  • CO is effective output capacitance.
Equation 14. GUID-40042B99-2E4B-4FB5-841E-CBDCBDB44AAE-low.gif

where

  • RESR is the equivalent series resistance of the output capacitor.
Equation 15. GUID-D7B1D6F4-545B-43D5-9A54-541591254435-low.gif

The COMP pin is the output of the internal transconductance amplifier. Equation 16 shows the small signal transfer function of compensation network.

Equation 16. GUID-A50F779C-2EB6-4C1B-AD11-7F18AE3F0A57-low.gif

where

  • GEA is the transconductance of the amplifier, which is 240uS.
  • REA is the output resistance of the amplifier, which is 100MΩ.
  • VREF is the reference voltage at the FB pin.
  • VOUT is the output voltage.
  • ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
  • ƒCOMZ is the zero's frequency of the compensation network.

The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.

Then set the value of RC, CC, and CP (in Figure 7-1) by following these equations.

Equation 17. GUID-2F3C8BF6-096A-4EA8-BACB-BBE5D0E2C7EB-low.gif

where

  • ƒC is the selected crossover frequency.

The value of CC can be set by Equation 18.

Equation 18. GUID-84FAD511-C358-4ACC-8B8D-465DA8FBEE24-low.gif

The value of CP can be set by Equation 19.

Equation 19. GUID-B81C49DD-D942-4950-BBBB-7D673B149BE8-low.gif

If the calculated value of CP is less than 10pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10dB gain margin eliminates output voltage ringing during the line and load transient.