JAJSSX0B January   2022  – January 2024 TPS61376

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VCC Power Supply
      2. 6.3.2 Enable and Programmable UVLO
      3. 6.3.3 Soft Start and Inrush Current Control During Start-Up
      4. 6.3.4 Switching Frequency
      5. 6.3.5 Adjustable input average Current Limit
      6. 6.3.6 Shut Down and Load Disconnect
      7. 6.3.7 Overvoltage Protection
      8. 6.3.8 Output Short Protection
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Auto PFM Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap Capacitor Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Output Capacitor Selection
        6. 7.2.2.6 Diode Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20231128-SS0I-FGT8-R2TW-JBF3VSLWQDJB-low.svg Figure 4-1 13-Pin RYH VQFN Package (Top View)
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NUMBER
VIN 1 I IC power supply input
EN/UVLO 2 I Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider.
ISEL 3 I Scale the ISO FET to improve input average current limit accuracy and adjust peak switching current limit value.

ISEL = low when setting Ilimit ≤ 750mA

ISEL = high, when setting Ilimit > 750mA
VOUT 4 PWR Boost converter output
VP 5 PWR Drain of the ISO MOSFET
SW 6 PWR The switching node pin. It is connected to the drain of the internal low-side power MOSFET and the source of the internal ISO power MOSFET.
PGND 7 PWR Power ground of the IC
FB 8 I Output voltage feedback pin. Connect to the center tape of a resistor divider to program the output voltage.
COMP 9 O Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin.
ILIM 10 I Input average current limit setting pin. Use a resistor between this pin and AGND to set the desired input average current limit threshold.
VCC 11 O Output of the internal regulator. A ceramic capacitor of more than 1μF is required between this pin and AGND.
AGND 12 PWR Analog ground of the IC
BOOT 13 O Power supply for ISO MOSFET gate driver. A ceramic capacitor of more than 0.47μF must be connected between this pin and the SW pin.