JAJSHO1C May   2014  – July 2019 TPS62150A-Q1 , TPS62152A-Q1 , TPS62153A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Pulse Width Modulation (PWM) Operation
      2. 9.3.2  Power Save Mode Operation
      3. 9.3.3  100% Duty-Cycle Operation
      4. 9.3.4  Enable / Shutdown (EN)
      5. 9.3.5  Soft Start / Tracking (SS/TR)
      6. 9.3.6  Current Limit And Short Circuit Protection
      7. 9.3.7  Power Good (PG)
      8. 9.3.8  Pin-Selectable Output Voltage (DEF)
      9. 9.3.9  Frequency Selection (FSW)
      10. 9.3.10 Under Voltage Lockout (UVLO)
      11. 9.3.11 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation above TJ=125°C
      2. 9.4.2 Operation with VIN < 3V
      3. 9.4.3 Operation with separate EN Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS62150A-Q1 Point-Of-Load Step Down Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2 Programming The Output Voltage
          3. 10.2.1.2.3 External Component Selection
          4. 10.2.1.2.4 Inductor Selection
          5. 10.2.1.2.5 Output Capacitor
          6. 10.2.1.2.6 Input Capacitor
          7. 10.2.1.2.7 Soft Start Capacitor
          8. 10.2.1.2.8 Tracking Function
          9. 10.2.1.2.9 Output Filter And Loop Stability
        3. 10.2.1.3 Application Curves
      2. 10.2.2 System Examples
        1. 10.2.2.1 Regulated Power LED Supply
        2. 10.2.2.2 Inverting Power Supply
        3. 10.2.2.3 Active Output Discharge
        4. 10.2.2.4 Various Output Voltages
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGT|16
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View
TPS62150A-Q1 TPS62152A-Q1 TPS62153A-Q1 SLVSCC3_pinout.gif

Pin Functions

PIN(1) I/O DESCRIPTION
NAME NO.
SW 1,2,3 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor.
PG 4 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires pull-up resistor)
FB 5 I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to connect FB to AGND on fixed output voltage versions for improved thermal performance.
AGND 6 Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
FSW 7 I Switching Frequency Select (Low=2.5MHz, High=1.25MHz for typical operation)(2)
DEF 8 I Output Voltage Scaling (Low = nominal, High = nominal + 5%)(2)
SS/TR 9 I Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing.
AVIN 10 I Supply voltage for control circuitry. Connect to same source as PVIN.
PVIN 11,12 I Supply voltage for power stage. Connect to same source as AVIN.
EN 13 I Enable input (High = enabled, Low = disabled)(2)
VOS 14 I Output voltage sense pin and connection for the control loop circuitry.
PGND 15,16 Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Exposed Thermal Pad Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane(3). Must be soldered to achieve appropriate power dissipation and mechanical reliability.
(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.
(2) An internal pull-down resistor keeps logic level low, if pin is floating.
(3) See Figure 50.