SLVS763E June   2007  – July 2015 TPS62260 , TPS62261 , TPS62262 , TPS62263

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Voltage Positioning
      2. 8.3.2 Undervoltage Lockout
      3. 8.3.3 Mode Selection
      4. 8.3.4 Enable
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft-Start
      2. 8.4.2 Power Save Mode
      3. 8.4.3 100% Duty Cycle Low Dropout Operation
      4. 8.4.4 Short-Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS62260, Adjustable 1.5-V Output
      2. 9.3.2 TPS62262, Fixed 1.2-V Output
      3. 9.3.3 TPS62261, Fixed 1.8-V Output
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MAX MIN UNIT
VIN Input voltage (2) –0.3 7 V
Voltage at EN, MODE –0.3 VIN +0.3 ≤ 7
Voltage on SW –0.3 7
Peak output current Internally limited A
TJ Maximum operating junction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Supply voltage 2 6 V
Output voltage range for adjustable voltage 0.6 VIN V
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS62260, TPS62261, TPS62262, TPS62263 TPS62260, TPS62262 UNIT
DRV [WSON] DDC [SOT]
6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 67.8 226.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 88.5 40.7 °C/W
RθJB Junction-to-board thermal resistance 37.2 48.8 °C/W
ψJT Junction-to-top characterization parameter 2.0 0.5 °C/W
ψJB Junction-to-board characterization parameter 37.6 48.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.9 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V. External components CIN = 4.7 μF 0603, COUT = 10 μF 0603, L = 2.2 μH, see the parameter measurement information.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 2.3 6 V
IOUT Output current VIN 2.5 V to 6 V 600 mA
VIN 2.3 V to 2.5 V 300
VIN 2 V to 2.3 V 150
IQ Operating quiescent current IOUT = 0 mA, PFM mode enabled
(MODE = GND) device not switching		 15 μA
IOUT = 0 mA, PFM mode enabled
(MODE = GND) device switching, VOUT = 1.8 V, see (1)		 18.5
IOUT = 0 mA, switching with no load
(MODE = VIN), PWM operation, VOUT = 1.8 V,
VIN = 3 V		 3.8 mA
ISD Shutdown current EN = GND 0.1 1 μA
UVLO Undervoltage lockout threshold Falling 1.85 V
Rising 1.95
ENABLE, MODE
VIH High level input voltage, EN, MODE 2 V ≤ VIN ≤ 6 V 1 VIN V
VIL Low level input voltage, EN, MODE 2 V ≤ VIN ≤ 6 V 0 0.4 V
IIN Input bias current, EN, MODE EN, MODE = GND or VIN 0.01 1 μA
POWER SWITCH
RDS(on) High side MOSFET on-resistance VIN = VGS = 3.6 V, TA = 25°C 240 480 mΩ
Low side MOSFET on-resistance 185 380
ILIMF Forward current limit MOSFET high side and low side VIN = VGS = 3.6 V 0.8 1 1.2 A
TSD Thermal shutdown Increasing junction temperature 140 °C
Thermal shutdown hysteresis Decreasing junction temperature 20
OSCILLATOR
fSW Oscillator frequency 2 V ≤ VIN ≤ 6 V 2 2.25 2.5 MHz
OUTPUT
VOUT Adjustable output voltage range 0.6 VIN V
VREF Reference voltage 600 mV
VFB Feedback voltage PWM mode MODE = VIN, PWM operation, for fixed output voltage versions VFB = VOUT,
2.5 V ≤ VIN  ≤ 6 V, 0 mA ≤ IOUT  ≤ 600 mA (3)		 –1.5% 0% 1.5%
Feedback voltage PFM mode MODE = GND, device in PFM mode, voltage positioning active(1) 1%
Load regulation PWM mode –0.5 %/A
tStart Up Start-up time Time from active EN to reach 95% of VOUT nominal 500 μs
tRamp VOUT ramp-up time Time to ramp from 5% to 95% of VOUT 250 μs
Ilkg Leakage current into SW pin VIN = 3.6 V, VIN = VOUT = VSW, EN = GND (2) 0.1 1 μA
(1) In PFM mode, the internal reference voltage is set to typ. 1.01 × VREF. See the parameter measurement information.
(2) In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin.
(3) For VIN = VOUT+ 0.6 V.

7.6 Typical Characteristics

TPS62260 TPS62261 TPS62262 TPS62263 isd_v_vin_lvs762.gifFigure 1. Shutdown Current Into VIN vs Input Voltage
TPS62260 TPS62261 TPS62262 TPS62263 rds_hs_vin_lvs762.gifFigure 3. Static Drain-Source On-State Resistance vs Input Voltage
TPS62260 TPS62261 TPS62262 TPS62263 iq_v_vin_lvs762.gifFigure 2. Quiescent Current vs Input Voltage
TPS62260 TPS62261 TPS62262 TPS62263 rds_ls_vin_lvs762.gifFigure 4. Static Drain-Source On-State Resistance vs Input Voltage