JAJS239G June   2007  – April 2018 TPS62290 , TPS62291 , TPS62293

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
      2.      効率と出力電流との関係
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Voltage Positioning
      2. 8.3.2 Enable
      3. 8.3.3 Mode Selection
      4. 8.3.4 Undervoltage Lockout
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft-Start
      2. 8.4.2 Power Save Mode
      3. 8.4.3 100% Duty Cycle Low Dropout Operation
      4. 8.4.4 Short-Circuit Protection
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The TPS6229x step down converters operate with typically 2.25-MHz fixed frequency pulse width modulation (PWM) mode at moderate to heavy load currents. At light load currents, the converters can automatically enter power save mode and operate then in pulse frequency modulation (PFM) mode.

During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high side MOSFET switch is turned on. The current flows now from the input capacitor via the high side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator also turns off the switch in case the current limit of the high side MOSFET switch is exceeded. After a dead time preventing shoot through current, the low side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the inductor to the output capacitor and to the load. It returns to the inductor through the low side MOSFET rectifier.

The next cycle is initiated by the clock signal again turning off the low side MOSFET rectifier and turning on the high side MOSFET switch.