JAJS360D January   2008  – October 2016 TPS62560 , TPS62561 , TPS62562

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Voltage Positioning
      2. 8.3.2 Undervoltage Lockout
      3. 8.3.3 Mode Selection
      4. 8.3.4 Enable
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft-Start
      2. 8.4.2 Power-Save Mode
        1. 8.4.2.1 100% Duty-Cycle Low-Dropout Operation
        2. 8.4.2.2 Short-Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
        2. 9.2.2.2 Output Filter Design (inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DDC Package
5-Pin SOT
Top View
TPS62560 TPS62561 TPS62562 po1_lvs815.gif
DRV Package
6-Pin SON
Top View
TPS62560 TPS62561 TPS62562 po1_lvs815_1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME No.
QFN-6		 No.
TSOT23-5
EN 4 3 I This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated.
FB 3 4 I Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In the fixed-output-voltage option, connect this terminal directly to the output capacitor.
GND 6 2 — GND supply pin
MODE 2 N/A I This pin is only available as a QFN package option. MODE pin = high forces the device to operate in the fixed-frequency PWM mode. MODE pin = low enables the power-save mode with automatic transition from PFM mode to fixed-frequency PWM mode.
SW 1 5 O This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between this pin and the output capacitor.
VIN 5 1 — VIN power-supply pin
Exposed Thermal Pad — N/A — Must be soldered to achieve appropriate power dissipation. Should be connected to GND.