JAJSHJ3D June   2019  – March 2020 TPS62840

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      効率と負荷電流の関係 (VOUT = 1.8V)
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Smart Enable and Shutdown
      2. 8.3.2 Soft Start
      3. 8.3.3 Mode Selection: Power-Save Mode (PFM/PWM) or Forced PWM Operation (FPWM)
      4. 8.3.4 Output Voltage Selection (VSET)
      5. 8.3.5 Undervoltage Lockout UVLO
      6. 8.3.6 Switch Current Limit / Short Circuit Protection
      7. 8.3.7 Output Voltage Discharge
      8. 8.3.8 Thermal Shutdown
      9. 8.3.9 STOP Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode Operation
      2. 8.4.2 Forced PWM Mode Operation
      3. 8.4.3 100% Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 サポート・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 Output Voltage Selection (VSET)

The output voltage is set with a single external resistor connected between the VSET pin and GND. Once the device has been enabled and the control logic as well as the reference system are powered up, an R2D (resistor to digital) conversion is started to detect the value of the external RSET resistor. A pre-defined fixed output voltage is set based on the RSET value. The output voltage is set once during the start-up delay phase of the device.

Once the output voltage is set, the R2D converter is turned off to avoid current flowing through RSET. Care must be taken that no parasitic current, capacitance, or both greater than 100 pF is present between the VSET and GND pins. This can cause false RSET readings and a faulty output voltage to be set. The R2D converter is designed to operate with resistor values out of E96 series. Table 1 shows the allowed RSET values.

Table 1. Output Voltage Setting, RSET Resistor

OUTPUT VOLTAGE SETTING VOUT [V] VSET RESISTANCE TO GND - E96 VALUES [Ω]
TPS62841YBG TPS62840YBG TPS62842DGR MIN NOM MAX
TPS62841DLC TPS62840DLC
TPS62841DGR
0.8 1.8 1.8 0 GND 0.01 k
0.85 1.9 2.0 0.87 k 0.909 k 0.95 k
0.9 2.0 2.2 1.67 k 1.74 k 1.81 k
0.95 2.1 2.4 2.76 k 2.87 k 2.98 k
1.0 2.2 2.5 4.15 k 4.32 k 4.49 k
1.05 2.3 2.6 5.80 k 6.04 k 6.28 k
1.1 2.4 2.7 8.11 k 8.45 k 8.79 k
1.15 2.5 2.8 11.04 k 11.5 k 11.96 k
1.2 2.6 2.9 15.17 k 15.8 k 16.43 k
1.25 2.7 3.0 20.64 k 21.5 k 22.36 k
1.3 2.8 3.1 27.55 k 28.7 k 29.85 k
1.35 2.9 3.2 36.77 k 38.3 k 39.83 k
1.4 3.0 3.3 50.21 k 52.3 k 54.39 k
1.45 3.1 3.4 68.64 k 71.5 k 74.36 k
1.5 3.2 3.49 97.92 k 102 k 106.08 k
1.55 3.3 3.6 256.32 k 267 k 277.68 k

The output voltage of the TPS62849 is internally set to 3.4 V. Connect VSET directly to GND for this device.