I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I²C-Bus Specification and User´s Manual, Revision 6, 4 April 2014). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A controller, usually a microcontroller or a digital signal processor, controls the bus. The controller is responsible for generating the SCL signal and device addresses. The controller also generates specific conditions that indicate the START and STOP of data transfer. A target receives or transmits data on the bus under control of the controller.

The TPS6287x-Q1 device operates as a target and supports the following data transfer modes, as defined in the I²C-Bus Specification: standard mode (100kbps) and fast mode (400kbps) and fast mode plus (1Mbps). The interface adds flexibility to the power supply design, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as the input voltage remains above 1.4V.

The data transfer protocol for standard and fast modes is exactly the same, therefore the modes are referred to as F/S-mode in this document. The device supports 7-bit addressing; general call addresses are not supported. The device 7-bt address is selected by the status of pin VSEL (see Table 8-5).

The protocol for high-speed mode is different from F/S-mode and is referred to as HS-mode.

TI recommends that the I²C controller initiates a STOP condition on the I²C bus after the initial power up of SDA and SCL pullup voltages to make sure of reset of the I²C engine.