JAJSS49 December   2023 TPS62916E

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Smart Config (S-CONF)
      2. 6.3.2  Device Enable (EN/SYNC)
      3. 6.3.3  Device Synchronization (EN/SYNC)
      4. 6.3.4  Spread Spectrum Modulation
      5. 6.3.5  Output Discharge
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Power-Good Output
      8. 6.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 6.3.9  Current Limit and Short-Circuit Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Fixed Frequency Pulse Width Modulation
      2. 6.4.2 Low Duty Cycle Operation
      3. 6.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 6.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Switching Frequency Selection
          2. 7.2.2.2.2 Inductor Selection for the First L-C Filter
          3. 7.2.2.2.3 Output Capacitor Selection
          4. 7.2.2.2.4 Ferrite Bead Selection for Second L-C Filter
          5. 7.2.2.2.5 Input Capacitor Selection
          6. 7.2.2.2.6 Setting the Output Voltage
          7. 7.2.2.2.7 NR/SS Capacitor Selection
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20220623-SS0I-FFB9-FJT8-R72QNJW91SLZ-low.svg Figure 4-1 14-Pin VQFN-HR, RPY Package (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME

2

NR/SS

O

 A capacitor connected to this pin sets the soft-start time and low frequency noise level of the device.

4

VO

I

 Output voltage sense pin. This pin must be connected directly after the first inductor.

8, 12

VIN

I

 Power supply input voltage pin

9, 11

PGND

 — Power ground connection

10

 SW O Switch pin of the power stage. Connect this pin to the start winding of the output inductor .

13

SW

O

Switch pin. Connect a capacitor from this pin to the BOOT pin.

7

EN/SYNC

I

 Enable, Disable pin including threshold-comparator. Connect to logic low to disable the device. Pull high to enable the device. This pin has an internal pulldown resistor of typically 500 kΩ when the device is disabled. Apply a clock to this pin to synchronize the device

14

BOOT

I

Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to SW.

1

PSNS

 —

Power sense ground, connect directly to GND plane

3

FB

O

 Feedback pin of the device

5

 PG O Open-drain power-good output. This pin is pulled to GND when VOUT is below the power-good threshold. this pin requires a pullup resistor to output a logic high. This pin can be left open or tied to GND if not used.

6

 S-CONF O Smart Configuration pin. This pin configures the operation modes of the device. See Table 6-1.
(1) I = input, O = output